[SI-LIST] : Power Noise
Jon Keeble ([email protected])
Thu, 18 Mar 1999 10:08:06 +1000
For mixed 5v / 3v3 systems I put another pair of planes close to the =
other side of the board, and bypass that paifrom that side. If the GND =
planes are on the inside, return current for all inner routing layers =
run in GND, making routing more flexible.
Don't forget that the bypass caps do more than provide a low impedance =
for power: they also, and equally importantly, provide a path for return =
current to get from the plane they return in to the appropriate power =
pin on the driver chip. Driving a high going edge means that return =
current has to get into the power pin of the driver: the only path is =
via a close by capacitor.
The other reason for enclosing tracks within a pair of GND planes means =
that vias don't require bypass
caps nearby to provide a path for return currents.
So, I place caps in an array around the chip, not being concerned about =
how close to the power pins they are, no more than about an inch apart.
Placement of caps has more effect on the length of path the return =
signal has to traverse. How different this path is governs the size of =
the loop and how much raditation results. (Another very good reason to =
provide as much C between planes as possible).
BTW, it doesn't really matter whether the bypass cap looks like a C or =
L, as long as the magnitude of Z is low.
The effectiveness of small SM caps relates to the ratio of length to =
width: the 0805 package is the best of the normal packages.
There is a number of low inductance cap designs. One is 0612 (the =
opposite of 1206) that provide a better ration of L/W.
Another is actually multiple caps with the current flowing in opposite =
directions to reduced inductance.
Jon Keeble
------=_NextPart_000_00F0_01BE7127.37C56860
Content-Type: text/html;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD W3 HTML//EN">
>Now, if the highest inductance part of the path is the pad/via, =
would=20
that
>favor running (wide) traces from the cap directly to the =
device,=20
since that
>eliminates two vias between the cap and the device? A =
wide,=20
short path only
>has a few nH inductance (I think).
Hi=20
Doug
There's no argument that minimising =
the length,=20
and maximising the width, of the connection from C to planes minimises =
the=20
inductance. Same goes for connecting component pads to planes. Both are=20
important.
Between connections on a plane there =
is really a=20
very low impedance.
The C between planes can be a very useful component =
as well,=20
if they placed close together.
From the above, I layup my boards so that the power =
planes are=20
adjacent, and close to one surface of the board, and place the bypass =
caps on=20
that side. For a .060" thick board, if the planes are in the =
middle, that=20
adds a total of .060" trace length (often through a narrow via) =
which is a=20
much larger inductance.
For mixed 5v / 3v3 systems I put another pair of =
planes close=20
to the other side of the board, and bypass that paifrom that side. If =
the GND=20
planes are on the inside, return current for all inner routing layers =
run in=20
GND, making routing more flexible.
Don't forget =
that the bypass=20
caps do more than provide a low impedance for power: they also, and =
equally=20
importantly, provide a path for return current to get from the plane =
they return=20
in to the appropriate power pin on the driver chip. Driving a high going =
edge=20
means that return current has to get into the power pin of the driver: =
the only=20
path is via a close by capacitor.
The other reason for enclosing =
tracks within a=20
pair of GND planes means that vias don't require bypass
caps nearby to provide a path =
for =20
return currents.
So, I place caps in an array around the chip, not =
being=20
concerned about how close to the power pins they are, no more than about =
an inch=20
apart.
Placement of caps has more effect on =
the length=20
of path the return signal has to traverse. How different this path is =
governs=20
the size of the loop and how much raditation results. (Another very good =
reason=20
to provide as much C between planes as possible).
BTW, it doesn't really matter =
whether the bypass=20
cap looks like a C or L, as long as the magnitude of Z is =
low.
The effectiveness of small SM caps relates to the =
ratio of=20
length to width: the 0805 package is the best of the normal=20
packages.
There is a number of low inductance cap designs. One =
is 0612=20
(the opposite of 1206) that provide a better ration of L/W.
Another is actually multiple caps with the current =
flowing in=20
opposite directions to reduced inductance.
Jon Keeble
------=_NextPart_000_00F0_01BE7127.37C56860--
**** To unsubscribe from si-list: send e-mail to [email protected]. In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu/si-list ****