No answers yet, only clarifications that might just add to the confusion
:-).
Are you counting on the (distributed) capacitance between planes A and
B to "close" the AC current loop? If this capacitance is not adequately low
impedance (compared to the extreme case of plane B not being present at all
, and the inductance loop is via-trace-via over plane A), the AC current has
to go
clear to the edge, and be connected to plane A and come back near the vias.
This has a time-of-flight consequence (therefore the spacing between planes
A & B
is important to keep the plane B to plane A impedance low).
On 2) If the planes A & B are truly infinite, and the locations of the
shorting wire
and / or voltage source truly remote, the "AC" current is not going to have
time to
go across plane B, down through the short, and back across the plane A. What
is
this "AC" or high frequency limit? A time of flight (with twice the extent
of the board)
calculation to the edge of the board ( or the nearest "effective" bypass
capacitor that
you may have) is probably a reasonable ball park.
*Above* this frequency, Plane B is effectively floating ( since the
transmission lines
are referenced to plane A) and floating planes are poorly handled by
electrostatic field
solvers (fudge by adding time of flight in Spice).
I am usually biased towards using partitioning-2D electrostatic field
solver /closed form -
Spice myself, but even so, this particular problem seems to be "doable"
with that particular
approach because there is a relatively low number of conductors involved.
I'm sure you've
figured though aout this, but in the field solver - plane B is really a
transmission line too
and you need to put in some approximations for current spreading in the
plane B/plane A
combination which will lower the planeB-plane A impedance .
Regards
Jay
> -----Original Message-----
> From: Leesa Noujeim [SMTP:[email protected]]
> Sent: Monday, March 15, 1999 9:30 AM
> To: [email protected]
> Subject: [SI-LIST] : signal propagation questions
>
> Hello SI experts,
>
> I have been struggling with the following problem,
> which is intended to have some of the
> characteristics of a printed circuit board
> signalling environment. I hope that someone
> here can help answer my questions, and/or
> point me to appropriate analysis techniques.
>
> Say we have one perfectly conducting plane, A. Parallel
> to A and at a distance t is a second perfectly
> conducting plane, B. Plane B is perforated by two
> small holes separated by a distance L. A thin wire
> (via) of length Lv passes through each hole.
> At the connection point between one via and plane A
> is an ideal voltage source with 50 ohm source impedance.
> At the connection point between the other via and
> plane A is a 50 ohm resistance. The two vias are joined
> by a thin strip (trace) of perfect conductor at
> height (Lv-t) above plane B. Both planes are infinite
> in extent; dielectric has relative permittivity of 1.
>
> ---------------------------------
> | |
> _____ | _____________________________ | _____ plane B
> | |
> | |
> Rs |
> ______V_______________________________R______ plane A
>
> I'd like to understand how this structure functions.
> In particular:
>
> 1) What is the voltage across the load resistor as
> a function of frequency if the source voltage
> is a 1 V sinusoid?
>
> 2) How does this change if I connect a wire between
> planes A and B at some remote location? ... if I
> add a DC voltage source in series with this wire?
>
> 3) What is the voltage across the load resistor if
> the source voltage is a square wave with a
> given rise/fall time?
>
> 4) For each of the above excitations, what is the
> current density on each conductor?
>
> 5) Can one say that above a certain frequency almost
> no current flows on plane A, and below another
> frequency almost no current flows on plane B?
> Is there a quick way to find these frequencies?
>
> 6) How sensitive are the answers to the above questions
> to via dimensions (wire and perforation diameters,
> plane thickness)?
>
> Should I use a full-wave field solver on the entire
> structure? Can I partition the problem into two vias
> and a transmission line, solve statically, then use
> spice? Or can I use some closed-form approximations?
>
> All suggestions are most welcome. Thanks!
>
>
> Leesa Noujeim
> Sun Microsystems
>
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