> I agree with Han's statement about series inductance and decoupling caps.
> However, a series inductor is still needed even when decoupling caps are
> properly placed.
>
> High frequency currents take the least inductive path. At the presence of
> decoupling capacitors across VCC/GND, there are two possible paths: through
> decoupling caps or through VCC/GND planes. Caps have series inductance
> (ESL), which makes them not as effective above their resonant frequencies.
> Therefore, to prevent high-f current to be sourced from VCC/GND planes
> causing EMI problems, one fix is to have a series inductor - typically a
> ferrite bead - to increase the VCC/GND loop inductance with respect to the
> decoupling cap ESL. This technique is generally applied to VCC, but could be
> extended to GND as well. The app note, "CK100 Clock Buffer Preliminary EMI
> Layout Guideline," available at http://developer.intel.com/ial/sdt/, gives
> such an example.
>
It looks like you are degrading the clock edge rates by increasing the impedance of the power distribution system, thus achieving EMI benefits. This technique will also help if the clock driver has a high crowbar current
(pull-up/pull-down structure conduction overlap). If you need precision, high edge rate clocks however, you would need a low impedance VCC/GND sandwich as a source for the high frequency currents.
If the clock outputs are single-ended, it looks like the clock signal return currents are flowing through the GND ferrites. Is the resulting CK_GND bounce not a problem?
> -Michael T. Zhang
> Platform Architecture Lab (PAL), Intel Corp
> (503) 264-2301
>
> -----Original Message-----
> From: [email protected] [mailto:[email protected]]
> Sent: Friday, March 05, 1999 8:06 AM
> To: [email protected]; [email protected]
> Cc: [email protected]
> Subject: Re: [SI-LIST] : A Question About Power Noise.
>
> The series addition of an inductor on the VCC line is an EMI type fix for
> very
> noisy IC's. This type of fix has worked for circuits for up to the 100MHz
> range. Their usefuleness for higher speeds may be doubtfull. Here is the
> theory.
> IC's with intensive di/dt requirements (e.g. clock generator and driver) may
> have the VCC fed with a series inductor to reduce Ldi/dt noise generation on
> the supply plane. Although this may appear counter-intuitive, the use of
> proper decoupling becomes now extremely critical for this to work. The
> decoupling capacitors will now have to provide all the di/dt to the VCC pin
> of
> the IC that would have come from the planes. That means that the decoupler
> cap
> must be adjacent to both the VCC and GND pins of the IC. Reducing the round
> trip inductance is a must so, for a j-leaded IC, the decoupler must be on
> same
> side as the IC with low inductance traces (short and wide). The vias to the
> planes are placed by the j-lead but not so as to affect the L of the trace
> to
> the cap.
> If proper decoupling had been designed in the first place, the need for an
> inductor would have been eliminated.
> Hans Mellberg
>
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