Responsibilities:
Designs and performs analog simulations of system level interconnects for PC
based platforms. Prepares I/O buffer models, transmission line models, and
packaging parasitic models for accurate correlated simulations. Performs
system level critical path timing, pre and post layout analyses. Uses
engineering judgment in data analysis to establish design process and CAD
tool
flow. U.S. typically requires a Bachelor's Degree in Elec. Eng. or Comp.
Eng.
+3 years experience, or a Master's Degree +2 years experience.
Skills:
Knowledge/experience with IBIS models and simulation/timing tools, such as
HSPICE, Quad Design, Cadence SpecctraQuest, Interconnectix, and Timing
Designer.
Extended coursework in electromagnetic fields and waves, and transmission
line
analysis. Knowledge of PC based system architecture, high speed bus
interfaces,
and high performance signaling techniques. This includes bus and system
timing,
signal integrity analysis, cross talk analysis, ground bounce analysis,
power
integrity analysis, as well as board layout techniques.
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