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EIAJ is mulling over a more accurate Spice model
By Stephan Ohr
EE Times
(01/20/99, 9:16 a.m. EDT)
SANTA CLARA, Calif. - The IBIS modeling consortium will formally consider an EIAJ alternative to its I/O buffer models to predict high-frequency anomalies-ground bounce, crosstalk, signal degradation and transmission line effects-on interconnects and lead frames on CPU and logic boards.
The Electronic Industries Association-Japan (EIAJ) has developed the challenge, Spice-based models called ?IMIC? for I/O Interface Models for Integrated Circuits. They are said to offer more-accurate modeling information for simulation than IBIS' own.
With EIAJ's models on the table, the IBIS (I/O Buffer Information Spec) consortium is uncertain whether to incorporate them into the proposed IBIS modeling process, bend the next IBIS standard revision toward EIAJ's thinking or simply leave it up to semiconductor and EDA tool vendors to decide which models to provide its customers. The consortium is expected to air some of these issues in presentations at DesignCon '99 the week of Feb.1 , and again at the IBIS Forum meeting the following week.
?We are working with the EIAJ, though we have no position statement yet,? said Bob Ross, a modeling engineer at Mentor Graphics Corp. (Wilsonville, Ore.), who serves as chairman of the American EIA's IBIS Forum. ?The IMIC standard has some potentially useful features, but we have to consider the trade-offs.?The EIAJ, which includes Japan's most powerful semiconductor manufacturers under the chairmanship of Hitachi's Dr. Hideki Fukuda, has developed an alternative to the IBIS buffer models used to analyze electromagnetic-compatibility (EMC) and signal-integrity problems on high-speed PC motherboards. The IMIC models are based on Spice, and describe a resistance-inductance-capacitance [RLC] network between power lines, grounds and pin-to-pin connections.
Though expressed as a simplified lookup table, IMIC provides a potentially more-accurate way to describe signal anomalies like ground bounce, agreed consultant Ed Sayre of Northeast Systems Associates (NESA, Stow, Mass.), chairman of the IBIS users group.
The IBIS behavioral models provide a much-simplified transistor driver model, RLC terminator, and V-I curves (voltage/ current rise-and-fall patterns) in the form of a lookup table. The richness of the V-I information is up to the model supplier. There is little that would allow a dynamic recalculation. Thus, the IBIS buffer models allow board makers to do a fast but crude analysis of signal-integrity issues.
Developed by a consortium of semiconductor and EDA tool vendors in 1993, the ?Input/Output Buffer Information Specification? (IBIS) allows the development of device models that preserve the proprietary nature of IC chip designs, while simultaneously providing information-rich models for signal-integrity and EMC analysis. The formation of the IBIS modeling philosophy was driven by Intel Corp., which had hoped to provide predictive information about the activity of I/O pins, yet to protect proprietary information (like process-specific variations) about its Pentium processors. ?IBIS models make it difficult to reverse-engineer transistor-level models,? Sayre said.
The IBIS format is supported by EDA tool vendors with board-level signal-integrity analysis tools, like Cadence, Mentor Graphics and HyperLinx (Redmond, Wash.) and semiconductor makers who provide IBIS models for their products. These include Actel, Advanced Micro Devices, Altera, American Microsystems, Fairchild Semiconductor, IBM Microelectronics, Integrated Device Technology, Intel, Lucent Technologies, Motorola, National Semiconductor, Siemens, Texas Instruments and Xilinx.
Yet, the IBIS modeling consortium has drawn criticism from the powerful semiconductor manufacturers in the EIAJ. Because they are deliberately muted, the IBIS models do not accurately model slew rates, ground bounce and the effects of complex lead frames, said the EIAJ. IBIS models, moreover, are slow to be updated to reflect faster clock rates, the association said. ?There are 'friction points',? acknowledged Sayre.
Combo spec?
Though the IBIS Forum has ratified Version 3.2 of the IBIS modeling spec, Ross doesn't rule out some combination of EIAJ thinking in the next version. Already, he said, the consortium has improved the open-drain model to improve accuracy in predictive simulations.
But in a paper to be presented at this week's DesignCon, Bob Haller, principal hardware engineer at Compaq Computer Corp. (Houston), warned against underestimating the accuracy of IBIS behavioral models. ?They can be both ends of the spectrum,? he said. ?Some are very accurate; some are off-base. You need to be careful.?
Haller suggests that his company has established criteria-?an accuracy specification?-for the semiconductor models it receives. He said vendors like Fairchild and Texas Instruments have given him accurate models, and have supported his com-pany's need to hold to the spec.
Moreover, any Spice representation will take its toll in computer run-time, reminds the IBIS users group's Sayre. ?A week's worth of Spice simulation is four days too long,? he said. IBIS modeling is ?friendlier? in that it will take minutes on a simulator, rather than hours as with Spice. ?With IBIS, you read in layout and routing files, and perform a fast computation for a large number of nets,? he explained. ?But it is meant to turn up egregious errors,? acknowledged Sayre, ?not minute variations.?
?One possibility is to merge IBIS and the more-detailed IMIC models by using IBIS as a 'calling mechanism' to import IMIC,? said Ross. ?But there are some technical concerns with this; they [the EIAJ members] have to clean up a few things.? This will be the discussion when the IBIS Forum meets Feb. 1.
Another possibility is for EDA tool vendors and semiconductor vendors to make their own decisions about IBIS or IMIC support. Fairchild Semiconductor, surmised Sayre, would likely provide both IBIS and IMIC models. But Motorola SPS, which has proprietary process information to protect, would give out only IBIS.
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