Re: [SI-LIST] : Vocabulary of Signal Integrity Degradations

[email protected]
Mon, 4 Jan 1999 09:05:18 -0500

Some thoughts on SI problems during design.

Signal Integrity

The challenge of controlling signal integrity is ever present in
designs that operate at speeds over 30-40 MHz. The signal integrity design
process includes technology characterization up front, which is necessary
to develop noise budgets, layout rules and circuit models. After the board
is routed it must be verified to ensure that all nets are free of
excessive noise. Identifying problem nets is only a part of the engineering
problem. These problems must be fixed in the design before a board is
built to prevent the design from being riddled with intermittent failures.

The following problems are related to signal integrity:

* Logic Hazards - occur when an input transition causes a glitch at the
output of a combinational logic circuit. In general, circuits
feeding pulse sensitive inputs (clock, enables, resets, and
clears) should be designed to be free of logic hazard.
* Timing Violations - a setup time (the time data must stabilize before
clock) or hold time (the time data must remain after clock)
violation of, for example, fipflop can produce a glitch.
Remember that a long path can delay the data leading to a setup
time violation; a short path can move the signal too quickly,
leading to hold time violation.
* Interconnect Problems The third means of getting the glitches, or in
general poor signal quality, is by means of inductive,
capacitive, and transmission lines effects of the package and
interconnect. All sorts of unwanted effects can ambush a pulse
as it travels from one chip to another - line impedance and
propagation delay effects, reflections, and crosstalk coupling.

From the above very important question have to be answered:
When Must Interconnects be treated as Transmission Lines?

It is customary to think of the load of a gate as a lumped
capacitor. This way of looking at things is valid only for slow
rise times and short interconnect lengths. If the interconnect
delay is greater than half the rise time, the circuit behaves as
a distributed load (network of transmission lines) and the
lumped capacitor viewpoint becomes inaccurate and misleading.
You have to know that printed circuit boards (PCB) and even the
larger multichip modules (MCM) fall into the distributed zone.
And while the dimensions on an integrated circuit (IC) are
small relative he rise time, even the interconnect on an IC
should be treated as a distributed RC network and as a lumped
capacitor. In other words when you compare the rise time with
the delay of the line and when the rise time is of the order of
or faster than two times the delay of the line, the line must be
treated as distributed transmission line.

Interconnect transmission line when:


So as the rise times get faster, more and more interconnects
must be treated as transmission lines.

* Simultaneous Switching Noise - refers to the ringing that occurs at the
output due to the synchronous switching of other outputs in the
same package. The effect has its origin in the parasitic
inductance of power and ground leads of the package.
That is why when connecting VCC and GND to IC's by using a trace
to a via; the trace must be at least 14 mils wide and should be
as short as possible (traces to GND can not exceed 1/8 of an
inch (125 mils).
* Logic Family - device characteristic affect signal integrity.
Sometimes the cleanest way to fix signal integrity problem is to
change the characteristics of the driver or receiver. This is
usually done by substituting it with different logic family.
Different circuit technologies behave quite differently when
driving the same transmission line. For example:
- HC Logic Family has low level of ringing and
undershoot with moderate rise time
-TTL Logic Family has low level of ringing with
small undershoot and soft (slow) rise time
-AC Logic Family has very high level of ringing and
undershoot with sharp rise time
-ALS Logic Family has low level of ringing with
small undershoot with moderate rise time
-ABT Logic Family has small level of ringing with
moderate undershoot and very sharp rise time
-F Logic Family has small level of ringing with
sharp undershoot and sharp rise time
* Busses They can present signal integrity problems.
The appearance of the waveform will depend on the location of
the driver. Drivers in the middle of the bus must drive in both
directions; such drivers see two normally unequal length
transmission lines in parallel. Note that termination cannot be
used if bus has any parts with weak drive. Terminating both
ends of net is possibility if no weak drivers. Different
solution may be to route bus as a ring. Although this solution
may not always be feasible, routing a bus as a closed ring could
improve the signal integrity on the bus. Now each driver thinks
it's in the middle of the bus. The two transmission lines
radiating from the driver in effect terminate each other. This
technique could be used on a single printed circuit board.

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