From: Binoj G. S. ([email protected])
Date: Wed Jun 06 2001 - 05:25:29 PDT
HELLO ALL,
I am using a differential pecl to ttl and ttl to differential pecl translator in my design in which the differential pecl o/p is using to drive one fo transceivers(hfbr 5903).As the fo transceiver i/p are in a different level I used capacitor coupling and biased the differential o\p at the fo i/p side.what I did is, biased the lines to middle of fo i/p (1.96v) with a thevenin termination which provides a 50 ohm impedance.
But what I read is that the termination voltage should be vcc-2,i.e. 1.3v(3.3-2).How can I satisfy both of this condition or I am doing something false?The fo I/p levels are as follows
vil min-1.49v vil max-1.825 vih min-2.135 vihmax-2.42
Thanks for replying
Binoj
----- Original Message -----
From: Michael Werner
To: Rengarajan S Krishnan
Cc: John Mackay ; 'Romeo Iacobut' ; si-list
Sent: Wednesday, June 06, 2001 3:28 PM
Subject: Re: [SI-LIST] : LVDS
The link is:
http://www.computer-design.com/Editorial/1999/03/0399a_case_for_low_voltage.html
M. W.
Rengarajan S Krishnan wrote:
Is an online version available? I dont have access to this magazine.
Thanks
Krishnan
John Mackay wrote:
hi Romeo
nice long LVDS article in Electronic Systems mag, March 1999, by
guys at National Semiconductor. Also, the canonical "MECL
Handbook" by Blood, of Motorola, establishes basic concepts.
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