From: Lynne Green ([email protected])
Date: Fri May 25 2001 - 17:33:20 PDT
Wherever power/ground run in "parallel", (over the IO or
in the core), you can use whatever layers are not used
for routing for caps (such as M2=P,M3=G,M4=P,M5=G).
Interleaved metal can provide a lot of capacitance when
the oxides are thin.
Some designers put similar structures in the core region
(on P1/P2/M1/M2) where empty space occurs (unused
**** To unsubscribe from si-list or si-list-digest: send e-mail to
[email protected] In the BODY of message put: UNSUBSCRIBE
si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
si-list archives are accessible at http://www.qsl.net/wb6tpu
This archive was generated by hypermail 2b29 : Thu Jun 21 2001 - 10:12:09 PDT