Re: [SI-LIST] : On chip decoupling

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From: D. C. Sessions ([email protected])
Date: Fri May 25 2001 - 08:30:49 PDT

On Friday 25 May 2001 08:19, Tom Zimmerman wrote:
> ----- Original Message -----
> From: "D. C. Sessions" <[email protected]>
> To: <[email protected]>
> Sent: Friday, May 25, 2001 9:48 AM
> Subject: Re: [SI-LIST] : On chip decoupling
> > Far and away the most effective capacitance is gate oxide capacitors. Anything
> > else has too much ESR to be useful. Long-channel P and N devices (not too
> > long or the ESR bug bites) both work fine; just tie the P gate to Vss and the source
> > and drain to Vdd (and vice versa for N). You do need good supply ESD protection,
> > but anything between the gates and the rails ruins the high-frequency performance.
> I'm not sure what you mean by "between the gates and the rails." Which
> gates? Could you clarify?

P-channel gate to Vss, N-channel gate to Vdd.
P-channel source and drain to Vdd.
N-channel source and drain to Vss.

> Also, how do you limit the Q to avoid ringing on the supply? Does the
> inherent resistance of the long channel device accomplish this?

Series resistance to limit Q is counterproductive in terms of limiting
transient supply drop. Shunt RC, on the other hand, does a lovely
job with ringing reduction. Since the resonant frequency of the LC
system is much lower than the operating frequency, you can hang
large amounts of high-ESR capacitance on there and get the necessary

Conveniently, well-to-bulk capacitance has quite high ESR, and it
even has a largish range of RC products depending on geometry.
Add the plethora of quiescent gates that are all over the place and
you have a pretty low Q system. (Also don't forget that the net logic
load acts effectively resistive for frequencies below the clock rate
due to I=VFC).

| The race is not always to the swift, nor the battle to the strong. |
| Because the slow, feeble old codgers like me cheat.                |
+--------------- D. C. Sessions <[email protected]> --------------+

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