Re: [SI-LIST] : Daisy Chain topology - termination schemes

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From: selvaraj subramanian ([email protected])
Date: Sun May 13 2001 - 23:29:10 PDT

Hi Rede,

Thanks for your mail.

Here is the info of my topology.

1. Clock Frequency: 66MHz
2. Clock Amplitude : 3.3V
3. Type of Driver : LVTTL
4. Number of Drops : 6
5. Z0 of trace : 50 ohms
6. Length of each link : 3 inches
7. Type of inputs : LVTTL

thanks in advance.

regards,
Selva
  ----- Original Message -----
  From: Rede, James
  To: '[email protected]'
  Sent: Friday, May 11, 2001 6:47 PM
  Subject: RE: [SI-LIST] : Daisy Chain topology - termination schemes

  Hi Selva,
   
  I may be able to help you with your daisy-chain design.
  I have done a lot of work with this topology and know a few tricks.
  Please give me the following details:
  1) Clock Frequency _______________
  2) Clock Amplitude________________
  3) Type of Driver__________________
  4) Number of Drops________________
  5) Zo of trace_____________________
  6) Length of Each Link_____________
  7) Type of Inputs__________________
   
  Once I have this data, I will be able to tell what may work.
   
  Best Regards,
   
  JJ Rede
  Taqua Systems
  Hyannis MA
    -----Original Message-----
    From: selvaraj subramanian [mailto:[email protected]]
    Sent: Friday, May 11, 2001 2:17 AM
    To: [email protected]
    Subject: [SI-LIST] : Daisy Chain topology - termination schemes

    Hello all,

    My simulations using XTK for most of the daisy chain topology is showing non-monotonicity on both the edges of the data/signal. I tried different termination strategies to remove the kink. But couln't.

    What I saw was that the worst affected load is the first load from the driver?

    Suggest me how to remove the non-monotonicity while using the daisy chain topology and is it ok if I bring that kink within the threshold levels.

    thanks in advance.

    regards,
    Selva

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