From: Greim, Michael ([email protected])
Date: Thu May 10 2001 - 07:49:02 PDT
Hi Rahul et al,
Calculating buffer delays in the model editor is really
Once in the model editor you will see the pins and the
associated IO cells. clicking on an IO cell will cause
the IBIS device pin data to come up. At the bottom of
this window is the buffer delays button. Clicking on this
will cause the buffer delays window to come up. If the
six boxes at the bottom are empty there are no delays and
they will have to be calculated.
One is best served clicking on the edit IO cell button to
make sure that the test circuit is correct (equivalent with
the datasheet). Remember that Vmeasure may move across voltage
While input threshold is not part of a devices buffer delay
measurement it is part of timing calculation so for input
cells, remember to validate the input threshold values.
When you are through checking/editing these values "OK" out
of the box. If you made changes you will probably be prompted
to recalculate buffer delays. Once you return to the buffer
delays window you can click on the measure delays button and
it will calculate the delay for the output buffer.
Once this is done OK out of all the windows until you return
to the ibis model editor. Once all the individual cells are
sanitized you can calculate delays for the entire device.
At the bottom of the model editor window, clicking the measure
delays button will calculate the delays for the whole device.
Once you OK out of this window the data will be saved in the
dml file. The format of this is shown below.
--------------------Cut Here ------------------------------
(C 1.32e-012 )
(L 4.9e-009 )
(R 0.55 )
(WireNumber 2 )
(signal DQ0 )
(signal_model K4S560832B_DQ_PIN )
(minimum 8.49506e-010 )
(typical 9.83987e-010 )
(maximum 1.23966e-009 ) )
(minimum 1.18247e-009 )
(typical 1.16503e-009 )
(maximum 1.3097e-009 ) ) ) ) )
------------------- Cut Here -------------------------------
I hope this proves to be helpful.
Michael C. Greim Sonus Networks
[email protected] 978-589-8336
Making the world safe for digital signals everywhere
And all this science I don't understand
It's just my job six days a week
The time is gone. The email's over
Thought I'd something more to say......
From: whiz kid [mailto:[email protected]]
Sent: Wednesday, May 09, 2001 9:24 PM
To: [email protected]
Subject: RE: [SI-LIST] : specctraquest waveform sims fail with design
link and buffer delays on the fly......
I have a question for you.I would really appreciate if
you can explain me how to calculate the buffer delays
in the model editor.
Thanks in advance.
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