From: Dagostino, Tom ([email protected])
Date: Mon Apr 30 2001 - 09:15:12 PDT
I've seen a lot of different standards for measuring edge rates. When I was
designing scopes we always used the 10 to 90% metric, thus the defaults on
your scope. If I remember correctly, we were looking for critically damped
2 pole Guassian response in the scope. The edge was fairly linear between
the 10 and 90% points. When ECL first appeared in the 60's Motorola used 20
to 80% measurements because there was a fast slew between those points but
ECL tended to slowly attain its final values. As D. C. Sessions points out
for a logic gate the time between the input thresholds is important but that
measurement gives no indication of the impact on SI issues. I've also seen
max dV/dT numbers given for a part. IBIS standardized on the 20 to 80%
means of modeling edge rates for the ramp data.
Rates of 180 psec for 0.7 volts is really not that fast. The faster parts
that I have seen are more like 50 psec for that voltage change.
Tom Dagostino
IBIS and Tau Modeling Manager
SDD
Mentor Graphics Corp.
503-685-1613
[email protected]
-----Original Message-----
From: D. C. Sessions [mailto:[email protected]]
Sent: Saturday, April 28, 2001 7:34 AM
To: [email protected]
Subject: Re: [SI-LIST] : RE: Edge rates
On Friday 27 April 2001 11:59, Doug Hopperstad wrote:
> I have a question regarding edge rates. Is there a standard for the edge
> rate points, i.e. 90%/10% or a specific voltage point like 2v, 0.8 v? I
have
> some data sheets that indicate the edge rates are determined by the
percent
> method and other data sheets (SSTL) that call out for ViH/ViL point for
the
> markers. My Scope is defaulted at the 90/10 percent setting and if I use
it,
> I get fairly good timing numbers of ~ 600pS. However, the vendor of the
> component is calling out to use Vref +/- 0.35 volts with Vref normally at
> 1.25 volts. If I measure the edges in the lab with that method, my timing
is
> an insane 180pS per the 0.7 volt delta. My overshoot is not reflective of
> the faster edge rates.
>
> Can anyone provide some insight into the different procedures called out
in
> the design specification books?
Well, for starts you can forget about 0.8/2.0 unless you're actually using
bipolar devices with Schottky inputs. Which I doubt.
The SSTL (and other recent JEDEC) specs call for edge rates between
the AC thresholds because that's what the receivers actually care about.
In general, there's an input amplitude/risetime combination that gets about
as much receiver performance as you're going to; after that something else
becomes the dominant performance limiter. Receiver delay becomes very
messy to estimate once you violate that condition; the IBIS committee tried
for almost two years to come up with a way to characterize input delays and
effectively gave up in favor of what amounts to circuit simulation (still
not
complete.)
All of which is irrelevant to "edge rate" as a signal-integrity issue.
Despite other comments, that really does depend primarily on percentages
since you're trying to determine the timescale of a linear process (that is,
the time answer is independent of voltage scaling.)
-- | The race is not always to the swift, nor the battle to the strong. | | Because the slow, feeble old codgers like me cheat. | +--------------- D. C. Sessions <[email protected]> --------------+**** To unsubscribe from si-list or si-list-digest: send e-mail to [email protected]. In the BODY of message put: UNSUBSCRIBE si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu ****
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