Re: [SI-LIST] : Attenuation on a PCB trace

About this list Date view Thread view Subject view Author view

From: D. C. Sessions ([email protected])
Date: Tue Apr 24 2001 - 11:09:24 PDT

On Tuesday 24 April 2001 07:12, Degerstrom, Michael J. wrote:

> My approach for incorporating very high speed signals
> is to route them in microstrip to avoid vias and so that
> I can get a wider line than stripline while maintaining
> a 50 ohm environment. I would like to hear from others
> as to the following:

The flip side is that the area around active circuits is so congested
that you may not have the option of running wide traces. (You may
also not be able to route in and out on one layer.) Putting vias in
the ball land is a halfway-reasonable solution and gets you down
to inner layers with moderate pain (still have that stupid stub unless
you use blind vias.)

Before anyone asks how congested you're going to get at serious
speeds, I'll point out that I have RFPs for ICs with over 128 lanes
(2 wires/lane) running 320 ps data cycles. There are more-or-less
standard interfaces headed that direction.

| The race is not always to the swift, nor the battle to the strong. |
| Because the slow, feeble old codgers like me cheat.                |
+--------------- D. C. Sessions <[email protected]> --------------+

**** To unsubscribe from si-list or si-list-digest: send e-mail to [email protected] In the BODY of message put: UNSUBSCRIBE si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP. si-list archives are accessible at ****

About this list Date view Thread view Subject view Author view

This archive was generated by hypermail 2b29 : Thu Jun 21 2001 - 10:11:42 PDT