RE: [SI-LIST] : implementing delay on board

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From: Zabinski, Patrick J. ([email protected])
Date: Wed Apr 11 2001 - 10:38:30 PDT


Saeen,

Two simple things to try:

        * adjust your .TRAN statement for a finer time-step
          (e.g., 5 or 10 psec)

        * include a .OPTION DELMAX=5ps statement

Pat

> Hello SI gurus,
>
> I want to delay some clocks relative to data on my board to take care
> of setup and hold time requirements of the receiver. I am using
> Hspice and the topology is
>
> Driver ---- Transmission line ---- Receiver
>
> The source impedence of the driver is pretty close to the impedence of
> the transmission line, therefore, no series termination is required.
> (as per my simulations using Hspice). The risetime of the driver is
> approximately 600 ps (0-100%). The propdelay of the transmission line
> comes out to be 165 ps/inch.
>
> I am using Hspice version 2000.2 and am using ideal transmission line.
> (T elements). My understanding was, if the length of the transmission
> line is longer than twice the rise time, any extra delay I add should
> appear as pure delay (neglecting any degradation in risetime).
> But, when I do a spice run on trace lengths from 10 inch to 25 inch
> and measure the the delay between waveforms of different lengths,
> the results do not appear uniform. For example, I expect to see
> the delay between a 15 inch tline and 16inch tline to be 165ps, but it
> is not so. Sometimes it is more and sometimes it is less (across the
> length sweep 10-25inch). What could be the reason for this????
>
> One more thing, the signal has a 50% duty cycle and I am measuring the
> delay after 10 cycles (just to let the initial transitions die out).
> The frequency is 125MHz.
>
>
>
> Any inputs would be really appreciated...
>
> Saeen
>
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