[SI-LIST] : need advice on IBIS i/o model enable signal, Low works, High gives error

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From: Fred U. Rosenberger ([email protected])
Date: Tue Mar 27 2001 - 09:49:02 PST

Am hoping some one can give me a little advice on IBIS I/O enable.
My original message is below but the listserver apparently rejected it
because of
the HELP, either in the subject or first line of message. I need something
protect me from programs trying to protect me!

HELP! I am probably doing something dumb, I just don't know
what dumb thing it is. Am trying to simulate with Xilinx
.ibs models. Have the following instantiation. Works ok as
is but when I try to disable the driver by changing "Low" to
"High" I get the error message listed below. I expect the
problem is obvious to anyone with experience here but it
certainly is frustrating me.



* Changing Low to High in following (to disable the output) causes
* HSPICE to fail with the error message:
* ** error**: iob_loads3:9712:
* Number of enable voltage sources in IOB = 0
B_P66_max nd_ps_max nd_gc_max t_line_max_in pci66_in Low Rec1
+ file = 'virtexe.ibs'
+ model = 'LVCMOS25'
+ typ=max power=on
+ buffer=3

 Vlow Low 0
* have tried both 1 and 3.3 for following source
Vhigh High 3.3


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