[SI-LIST] : Re: approximations for partial self inductance

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From: Sainath Nimmagadda ([email protected])
Date: Mon Mar 26 2001 - 09:21:54 PST

Dear all,

Remember this recent thread? Following up on this somewhat complex
topic, I went to select experts, thru personal communication, across the
globe. Let us share the responses received so far.

First response is from Dr. Franzon and the second from Dr. Wong. (Well,
that is the order in which I received them)

Dr. Franzon and Dr. Wong, we appreciate your taking time and thank you
for your valuable inputs.

Best regards,


Quite humbly, I simply reflect Howards first point (minimum energy).
Universe is lazy and current will take the path of least Impedance (ie.
complex power P=VI = ZI^2, so minimum power = miniumum Z), so that it
to do the least work.

Z=sqrt(R+jwL/G+jwC). Assuming current path does not affect C much, then

the current path takes the path of lowest R+jWL. If R is low, then that

becomes path of least L. Note, we are referring to total loop

Note that if R is high (e.g. on chip) then current does NOT take the
of lowest L, but least R+jwL - the current distn changes with frequency.

Also, note that this also explains the skin effect. When wL is high,
because w is high, then the current spreads to the skin to drop L at
the expense of R.

I hope that clarifies. Feel free to forward this to the list. I am
travelling and in a touch of a rush.





In generally, current will flow through the path with the lowest

At low frequencies when the capacitors are open circuits and the
are short circuits, current will flow through the path with the lowest
RESISTANCE. This leads to problem such as current crowding around

At high frequencies when the capacitors and inductance can longer be
ignored, the path with the lowest IMPEDANCE may depend on the signal
frequency. For example, cross-talk capacitance may become low impedance

path and short out the current path, whereas inductive line may become
impedance and prevent current flow. To further complicate the issue,
inductance depends on the dimension of the current loop (i.e., the
line and the return path) and may be a function of frequency if the path

with the lowest impedance changes.

In principle, if one can generate the resistance, capacitance (including

self and cross-talk) and inductance (including self and mutual) matrixes

for the entire interconnect network, one can solve for the current
path. In practice, it will be too complex to model the entire chip.
can only model a small section of the chip at a time. This is
for the capacitance matrix since electric field is typically terminated
neighboring structures. Magnetic field, on the other hand, can reach
structures few hundred microns away, and hence greatly complicates the
inductance matrix.

At even higher frequencies, the lumped element approach (i.e., treating
interconnect as R, L and C) begins to breakdown, one will need to solve
Maxwell equations with EM solver. Phenomenon such as skin effect,
substrate loss can no longer be ignored.

I hope this explanation helps.



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