Re: [SI-LIST] : Another bypassing question, Rev 2

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From: [email protected]
Date: Mon Mar 26 2001 - 08:49:10 PST

> Subject: Re: [SI-LIST] : Another bypassing question, Rev 2

Hi all,

I've got another issue of concern. We're using 1mm BGAs with well over
500 pins (normal), and I've had one point of view presented to me. I've
(I'm a pcb layout person) almost always break out all the powers/gnds
thru the board to the bypass caps since there is no room near the chip
on the chip side (we like to socket these also. :) One engineer
mentioned breaking out the GND pins so they only go to the second layer
(internal GND plane, full plane, no splits). This will save a lot of
real estate on the far side of the board to bring the decoupling caps
that much closer to all the pwr pins. What might be the cons to this

BTW, the chips are fully utilized! There are no "no connected" pins.
They're either power/gnd or signal.



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Definitely near the chip side. The power/ground sandwich will provide the
maximum initial rate of charge delivery to the IC and the chip capacitors
charge delivery will be limited/slowed by the via inductance from the bottom
layer to the top layer. The IC pin inductance will be a deterrent in both


Michael L. Conn
Owner/Principal Consultant
Mikon Consulting

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