[SI-LIST] : SDRAM and SO-DIMM parallely routed?

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From: Matthias Mansfeld ([email protected])
Date: Thu Mar 22 2001 - 04:33:53 PST

Hello all,

application: a multimedia processor with SDRAM clocked at 100 MHz,
planned up to 133 or 143 MHz

the customer wants the design as follows: a SO-DIMM socket AND the
routing for placing 4 SSOP SDRAMs directly (then he could populate
the board with whatever uis best available).

The processor datasheet says "all routing has to be shorter than 100
mm, for 133 MHz shorter than 70 mm". There are 2 clock
outputs, each drives two memory chips and has currently series
termination with 33 Ohm. The whole stuff is preferrably routed with
50 Ohm impedance, an the capacitive load of eauch processor output is
30 pF including traces.

The topology the customer wants is: Processor<>SO-DIMM Socket <>

Only my thoughts "out of my stomach" (cannot simulate this stuff):

If we place the SDRAMs only, then it would probably run well, because
the empty SO-DIMM socket is not a big problem. If the SO-DIMM is
used, we have many open traces to the pads of the not placed SDRAMS.
I can imagine to terminate all ends of the clock lines (true
Thevenin termination or s.th. similar instead of the currently used
serial resistor), but what could I do with the open adress/data
lines? I feel not comfortable with the idea to terminate all ends of
the address lines, and much worse, what to to with the data lines
with many sources?

I need more arguments to tell the customer that his idea will not
work properly. Or maybe someone did it and it ran well - then why?

Many thanks in advance. Regards
Matthias Mansfeld Elektronik
* Leiterplattenlayout, Bestueckung
Am Langhoelzl 11, 85540 Haar; Tel.: 089/4620 093-7, Fax: -8
Internet: http://www.mansfeld-elektronik.de

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