RE: [SI-LIST] : Inductance and Decoupling

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From: Zabinski, Patrick J. ([email protected])
Date: Tue Mar 13 2001 - 16:00:55 PST


For the most part, it looks like your analysis is on track.
I've performed similar analysis and ended up with roughly
the same number of caps.

That said, my original analysis targeted only 5% ripple
on VDD. However, depending upon how close you're riding
the timing and signal margins, you can generally push
the ripple a bit further and obtain acceptable performance.

The one factor I did not see included in your analysis is
the effects of ground/power planes. It's a touchy subject
on the SI-List, but most agree that it does offer some
useful capacitance.


> Hello, all
> I've recently started to calculate the de-coupling needed for
> efficiently supplying the spike currents needed by high-speed devices.
> During this task, I've encountered several ambiguities and
> results that
> I would like to share with you and perhaps hear some (useful) feedback
> from you.
> (1) I tried to evaluate the situation for one high-pin-count
> device with
> several buses connected to it (essentially a bus bridge). Even
> calculating for just one synchronous bus (with 144 bits overall) I
> arrived to the result that a few Amps (maybe even 5) are
> drawn when all
> or most of this bus bits change state. I wonder what will be
> the result
> if I would calculate for an additional bus (assuming it's synchronous
> with the first). And what about the internal changes? They might be
> contributing even more than the external bus! (e.g., the Motorola
> PowerPC HW manual states that 90% of the power consumption of this
> device is drawn internally, not externally).
> (2) I've also tried to calculate the inductance of the decoupling
> capacitors connections to the device. Even assuming a 40-mil
> wide 50-mil
> long trace right above a reference plane for the connection I
> have app.
> L=150-200pH. If I can't connect at least one of the capacitor pads so
> short I might have to do a direct connection via to a
> reference plane. I
> calculated this to have more than L=1nH!
> (3) I assumed the calculated peak currents change at a rate equivalent
> to the rise time of the device's output buffers. I don't know if it's
> true, but this seems to me the most logical thing to do. Even
> if I take
> it to be 2ns (1 ns is closer to worst-case, I believe), I get the
> result that I need 40 to 50 low-ESL decoupling capacitors for the case
> where L=1nH. Only if I succeed to connect the capacitors directly and
> close enough to both GND and VDD pins (L=150-200pH) do I get
> the result
> that it is sufficient to use 4-6 decoupling capacitors.
> (4) While calculating vias inductance, I've encountered 2 similar but
> different equations for this parameter. One is given by Mr. H. Johnson
> in his famous book (page 259), as follows:
> L=5d*{ln(2d/r)+1}nH.
> The other is given by Mr. Bogatin in one of his articles, and is:
> L=5d*{ln(2d/r)-3/4}nH.
> Can somwone explain the reason for the difference, or who is
> right? The
> difference starts to be quite critical when dealing with u-Vias!
> Thanks for anyone who makes the effort to read this email.
> --
> Itzhak Hirshtal
> Elta Electronics
> POB 330 Ashdod
> Israel 77102
> Tel: 972-8-8572841
> Fax: 972-8-8572978
> email: [email protected]

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