[SI-LIST] : 400MHz Source Synchronous Existance Proof?

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From: Bradley S Henson ([email protected])
Date: Thu Mar 08 2001 - 10:47:09 PST

For years I've been following IEEE 1596.3, SCI, various LVDS offerings, DDR
SRAMS etc. It would appear that given good engineering, we can send
parallel data with a clock over short distances ( a couple of inches) in a
point_to_point topology. RAMBUS seems to have faultered in the PC
environment mainly because of the multi_drop nature of the 3 memory cards,
although I'm sure there are many other opinions. I've personally done
source synch. to about 200MHz and serial to over 1GHz without great
problem. My question for the group is: Are 400MHz source synchronous
designs fairly common today or are they generally considered high-risk? Are
there any existance proofs fielded I can cite? In my case we will have
very fast (not CMOS) ASICs doing the sending and receiving, so elastic
buffers and appropriate attention to detail will be within our control. The
interface will be a low voltage swing differential, maybe PECL or CML.

Brad Henson, Raytheon

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