From: Larry Miller ([email protected])
Date: Mon Apr 30 2001 - 07:32:38 PDT
We used a goodly portion of connector pins for ground (which effectively
makes them stitching vias to connect the ground planes together right near
the scene of the crime) and also added stitching vias around in areas where
you could conceivably get resonant cavities at frequencies of interest, like
the edges of the boards... There were resonances up in the 4.5 to 6 GHz area
(the limit of our VNA) even so, but this is one place where the lossiness of
FR-4 is your friend. The resonant peaks were 40-50 dB down from the signal
levels of interest. (We ended up with about -8 dB @ 3.125 GHz relative to
"DC" in our particular case.)
I have never had much luck using bypass caps above a few hundred MHz (too
much inductance), and even buried capacitance seems to die out at about 1
GHz insofar as being effective. (I have never tried the 0.002" patented
buried plane gig.) So we use only GND for reference planes around striplines
and microstrips so that we can DC stitch them early and often. Yeah, it
usually adds a layer, maybe two, but when you are up to 14 layers already
the incremental cost is minimal.
Larry Miller
-----Original Message-----
From: Michael Nudelman [mailto:[email protected]]
Sent: Monday, April 30, 2001 6:44 AM
To: 'Javin Olson'; [email protected]
Subject: RE: [SI-LIST] : RE: 2.5 GHz in FR4
VCC and GND are equally noisy. And are equally good references. Imagine -
all your ref planes are VCCs. And just one is GND. What has changed?
Nothing.
The difference though is: if you use VCC/GND pairs as ref planes for each
hi-speed routing layer, you will have to put bunch of de-coupling capacitors
all over the board to provide for return currents along signals' runs i/o
putting bunch of vias connecting GNDs together.
What is more expensive I do not know. But the inductance of a cap as a
return path (cap itself and two vias) is higher than inductance of one via.
Mike.
-----Original Message-----
From: Javin Olson [mailto:[email protected]]
Sent: Monday, April 30, 2001 9:15 AM
To: [email protected]
Subject: FW: [SI-LIST] : RE: 2.5 GHz in FR4
Richard,
Your comment about making the via act like a transmission line is correct.
There are 2 ways that I know of to remove the stub caused by a via:
Blind vias - via stub is completely removed, but fabrication cost is
doubled.
Counterboring - basically this method drills out the rest of the via, and it
adds about 25% to fabrication
Both methods obviously hurt the testability access to the board. The other
thing you can do is remove all non-functional pads within the via to reduce
the overall capacitance of the via.
I have one question about stripline and referencing in general: Is there a
benefit to having your high-speed diff-pair signal layers sandwiched between
2 GND layers? Are power layers generally a noisier reference?
Any thoughts on my last 2 questions would be appreciated...
Javin Olson
Plexus Technology Group
Design Engineer
-----Original Message-----
From: [email protected]
[mailto:[email protected]]On Behalf Of [email protected]
Sent: Monday, April 30, 2001 5:56 AM
To: [email protected]; [email protected];
[email protected]
Subject: Re: [SI-LIST] : RE: 2.5 GHz in FR4
Larry,
After reading all of the replies to the 2.5GHz questiion, I can see the need
for using stripline to keep phaseshift constant on long runs. In trying to
make the stubs a part of the transmission line, wouldn't it be advisable to
utilise most of the via as part of the line by using the stripline located
on
the opposite side of a card from the IC?
Consider the 8 layer stackup shown here for clarification.
------- Sig and IC layer
------------- Plane
------- Sig
------------- Plane
------------- Plane
------- Sig 2.5 GHz stripline
------------- Plane
------ Sig
The stub resulting from the the unused portion of the via is reduced in
length. The trick would be to make the vias look like the transmission line
impedance.
Another thought--It seems like an imbedded microstrip line would possess
almost the same qualities of a stripline in terms of dielectric affecting
phaseshift. Can a card be made so that the vias would go only from the IC
layer to an imbedded microstrip layer directly below? This would get rid of
any stubs. What do you think?
Richard Ellison
972-569-8317
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