[SI-LIST] : address transition detection in SRAM?

From: Zabinski, Patrick J. ([email protected])
Date: Wed Apr 11 2001 - 04:15:35 PDT

• Next message: Neeraj Sharma: "Re: [SI-LIST] : Question to Jitter"
• Previous message: Kai Peters: "[SI-LIST] : Question to Jitter"

We are using (older) commercial asynch SRAM that has some
form of address transition detection circuitry.
In brief, the SRAM monitors the address bus. If bus does not
transition states, the SRAM goes to a low power state. When
a bit on the bus transitions states, the SRAM thinks something
is about to happen and wakes up.

Can anyone point me to references on address transition detection
circuitry such as this? We believe it might be causing us problems,
and I'd like to read up on how it works and any sensitivities
it might have. Any references to
app notes, papers, text books, etc. will be appreciated.

Pat

**** To unsubscribe from si-list or si-list-digest: send e-mail to
[email protected]. In the BODY of message put: UNSUBSCRIBE
si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
si-list archives are accessible at http://www.qsl.net/wb6tpu
****

• Next message: Neeraj Sharma: "Re: [SI-LIST] : Question to Jitter"
• Previous message: Kai Peters: "[SI-LIST] : Question to Jitter"

This archive was generated by hypermail 2b29 : Thu Jun 21 2001 - 10:11:30 PDT