Project: BERTE  - Bit Error Rate Test Equipment
Author: IK2PII Claudio Pozzi <ik2pii@amsat.org>

Abstract
          This paper describe a bit error rate test equipment. It was
          developed as tool for testing an high speed modem for digital
          radio communications. It uses two programmable logic devices
          PAL 22V10 (GAL are good replacements) and some common 74HCxx IC.
          The modem interface (data and clock) meets standard EIA RS422 
          but can be easily replaced. 
          BERTE includes a programmable clock generator and accept also 
          an external clock. It generates some useful bit sequences: all 
          zero, all one, alternating one and zero (square wave), 
          programmable pseudo-random bit sequence (up to 2exp24-1 bit 
          length). 
          Pressing a push button it's possible to insert an error bit into 
          the sequence. The error counter is external.

Acronyms
          BER   - bit error rate
          PRBS  - pseudo-random bit sequence
          IC    - integrated circuit
          bps   - bits per second
          SR    - shift register

Description
          The BERTE consists in two sections. The first one is the PRBS
          generator, the BERTE Pseudorandom Generator diagram in the file 
          ber_tx.ps is in poscript format. 
          XT1 is the clock oscillator.
          U1 is a programmable device PAL22V10. The source program for U1 
          is in the tx_ckg.pld file, the jedec file for device programming 
          is the tx_ckg.jed file.
          This IC is used as programmable clock divider. Pins 8,9,10,11 and 
          SW1 pattern defines the divide ratio. Actually I'm using a decimal 
          thumbswheel switch and U1 is programmed for nine bit rates, 
          starting from 2.048 Mbps down to 4096 bps. The position 9 of the 
          switch connect the output ckdiv to the external clock input ckext. 
          You can use an HEX switch (or perhaps 4 dip switches) and modify 
          tx_ckg file to have up to 16 bit rates. Pin 9 (chdiv) is the 
          divided clock. 
          U4, U3 and U7 are 74HC164 eight bit shift registers, connected 
          in series, and with U5A and U5B they constitute the PRBS
          generator. The ckdiv clock shifts the PRBS through the  24 bits
          shift register. You must connect two SR outputs (test pattern 
          selection) to x and y  U5A and U5B xor inputs. According to
          the outputs selected you can generate any PRBS up to 2exp24-1
          bit length. At the start-up may happens that the SR contains
          all the bits set to zero, in this case U5C, D1 and the associated 
          components insert some ones into the SR.
          The PRBS and ckdiv inverted by U5D are injected into U2, another
          PAL 22V10 acting as data/clock synchronizer. This IC performs also 
          some other tasks. It select, using the ptn0, ptn1 and ptn2 inputs,
          the data sequence coming out from the generator. The table shows
          how U2 works. Note that R6, R7 and R8 are pull-up resistors
          and that SW2 connects ptn to GND. The ptn pattern in the file
          tx_out_2.pld is inverted. The tx_out_2.jed file is the jedec file
          for U2 programming.

               +------+------+------+-----------------------------------+
               | ptn2 | ptn1 | ptn0 | sequence                          |
               +------+------+------+-----------------------------------+
               |  1   |  1   |  1   | all data are 0                    |
               |  1   |  1   |  0   | all data are 1                    |
               |  1   |  0   |  1   | sequence 10101010...(square wave) |
               |  1   |  0   |  0   | pseudo random sequence            |
               |  0   |  1   |  1   | pseudo random sequence with error |
               |  0   |  1   |  0   | to be defined                     |
               |  0   |  0   |  1   | to be defined                     |
               |  0   |  0   |  0   | to be defined                     |
               +------+------+------+-----------------------------------+
         
          Pressing the push button S1, one bit of the PRBS is inverted. 
          This inserts one error in the PRBS according that the pattern is 
          "011".
          U6 is the output interface. It meets the standard EIA RS422 and
          allows high speed and long distance connections. This IC can be 
          used as single end TTL interface, using only one of the 
          differential outputs and GND reference.

          The second section performs the error detector function. It 
          require the data and clock inputs from the modem under test. 
          The schematic diagram is in the ber_rx.ps file and is named BERTE 
          Error Detector.
          U6 is an 26LS32 IC, and meets the standard EIA RS422. It receive
          the data and clock signal from the modem and convert them to TTL
          level. The shift registers U1, U2 and U3 are connected in series
          and together with U3A perform the local PRBS generator function.
          Two of the test pattern pins of the SR must be connected to x 
          and y inputs of U3A in the same way as for the generator. 
          This PRBS generator is self synchronizing with the transmitted
          sequence. U3B compare the locally generated PRBS with the received
          sequence. For each erroneous bit received pin 6 of U3B outputs
          3 pulses. They are synchronized with clock by U4A an divided by 3
          in the following circuit. U3D act as buffer for output to the
          error counter circuit. I use an universal counter.

Pseudo random sequence
          For both the BERTE Pseudorandom Generator and the BERTE Error 
          Detector you must connect two outputs of the SR to the XOR inputs
          that provides the feedback to the input of the SR. Each output 
          (TAP) is numbered from 1 to 24. In the following table are showed 
          some CCITT recommended PRBS.
                                     
          ------------------+---------+-------------------------------------
          PRBS length       |  TAPs   |  notes
          ------------------+---------+-------------------------------------
          511      2exp9-1  |  5 & 9  |  recommended up to 14400 bit/s
          2047     2exp11-1 |  9 & 11 |  recommended in the range 48 kbit/s 
                            |         |  to 168 kbit/s
          32767    2exp15-1 | 14 & 15 |
          8388607  2exp20-1 | 18 & 23 |
          ------------------+---------+-------------------------------------
          
Error-ratio measuring range          
          The receiving equipment should be capable of measuring bit-error 
          ratios in the range 10exp-3 to 10exp-8.

Construction tips
          My working prototype is entirely wire-wrapped on a perforated 
          board 233x160 mm (double EUROCARD). The PRBS generator and PRBS 
          Error Detector can be on two separated board. I use two DIN 41617
          series connectors for inputs and outputs. Install one 100nF 
          capacitor near each IC and one 10 uF electrolytic capacitor for 
          each section. A 10 MHz dual channel oscilloscope can be useful
          for testing.

          Please don't ask for programmed PALs, I don't have a PAL 
          programmer.



References
     1.   Moser and Stover, Generation of Pseudo-Random Sequences for
          Spread Spectrum Systems, Microwave Journal MAY 1985, pp. 287-295
     2.   I2LYH Lucchi Gianfranco, Radio Rivista APR 1990 and MAY 1990
     3.   I2LYH Lucchi Gianfranco, private paper
     4.   I2VGO Verbena Gianfranco, private paper
     5.   The ARRL Handbook for Radio Amateurs 1999, chapter 12
     6.   The ARRL Spread Spectrum Sourcebook 1991, chapter 10 appendix A
