;*************************************************************************************************************************************
;*                                                                                                                                   *
;*                                  Serial input routine - using cascaded SR's (2x 74HC165)                                          *
;*                                           version 1.0.28 (aggggggh)  01 Feb 2010                                                  *
;*                                                Using devicde type PIC12F509                                                       *
;*                                                                                                                                   *
;*   (pin 1) Vdd +5vDC.                 (pin 8) Vss 0v/Gnd.                                                                          *
;*   (pin 2) GPIO_b5 PARALLEL LOAD      (pin 7) GPIO_b0 Unused                                                                       *
;*   (pin 3) GPIO_b4 CLOCK              (pin 6) GPIO_b1 Unused                                                                       *
;*   (pin 4) GPIO_b3 DATA in            (pin 5) GPIO_b2 Unused                                                                       *
;*                                                                                                                                   *
;* expanded I/O driver routine has been tested on PIC12F509, but should work on most of PIC range with appropriate memory mapping    *
;* for output shift register use CD4096, for input shift register use 74HC165, for CMOS/TTL converter use CD4504                     *
;* routine duration 218uS @ 4MHz                                                                                                     *
;*************************************************************************************************************************************

;*************************************
;*         System variables          *
;*************************************
	
EXP_IO_BIT_COUNT	equ	H'0007'			; Expanded I/O bit counter.
EXP_IO_BYTE_COUNT	equ	H'0008'			; Expanded I/O byte counter.
EXP_IO_TMP		equ	H'0009'			; Expanded I/O temporary byte.
EXP_IO_IN_BYTE_1	equ	H'000A'			; Expanded I/O input byte 1.
EXP_IO_IN_BYTE_2	equ	H'000B'			; Expanded I/O input byte 2.

;*************************************
;*         System variables          *
;*************************************

D_in			equ	H'0003'			; GPIO_b3   Input  - Input SR  - Data output
CLK			equ	H'0004'			; GPIO_b4   Output - Common    - Clock
LD			equ	H'0005'			; GPIO_b5   Output - Input SR  - /Load

;*************************************
;*  Expanded input driver routine    *
;*************************************

WEO			movlw	H'0008'			; Common I/O  Reset EXP_IO_BIT_COUNT - must be set to eight.
			movwf	EXP_IO_BIT_COUNT	; Common I/O    - "" -   
			movf	EXP_IO_BYTE_COUNT,W	; Common I/O  Check EXP_IO_OUT_BYTE_COUNT state
			btfss	STATUS,Z		; Common I/O    - "" -
			goto	WEO_#2			; Common I/O    - "" -
			movlw	H'0002'			; Common I/O      THEN Reset EXP_IO_OUT_BYTE_COUNT - number of SR's
			movwf	EXP_IO_BYTE_COUNT	; Common I/O        in this example we are using two cascaded SR's
			bcf	GPIO,LD			; Input       Initiate parallel load sequence...
			nop				; Input         - "" -
			bsf	GPIO,CLK		; Input         - "" -
			nop				; Input         - "" -
			bsf	GPIO,LD			; Input         - "" -
			bcf	GPIO,CLK		; Input         - "" -

WEO_#2
WEO_BIT			rrf     EXP_IO_TMP,F		; Common I/O  I/O bit processor - rotate right
WEO_BIT_#2
WEO_BIT_#3		btfss	GPIO,D_in		; Input       Input bit processor - test "GPIO,D_in"
			goto	WEO_BIT_#4		; Input       test "GPIO,D_in" state
			bsf	EXP_IO_TMP,b7		; Input           Then set "EXP_IO_TMP,b7" if "GPIO,D_in" is set
			goto	WEO_BIT_#5		; Input             - "" -
WEO_BIT_#4		bcf	EXP_IO_TMP,b7		; Input           ELSE clr "EXP_IO_TMP,b7" if "GPIO,D_in" is clr

WEO_BIT_#5		bsf	GPIO,CLK		; Common I/O  Generate a single clock pulse of 1uS duration…
			nop				; Common I/O    - "" -
			bcf	GPIO,CLK		; Common I/O    - "" -
			decfsz	EXP_IO_BIT_COUNT,F	; Common I/O  Decrement EXP_IO_BYTE_COUNT, and test for zero status.
			goto	WEO_BIT			; Common I/O   return to Bit processor (WEO_BIT) or, continue & finish... 

WEO_#8			movf	EXP_IO_BYTE_COUNT,W	; Input       Save data BYTE retrieved from SR's during the current cycle...
			addwf	PCL,F			; Input         - "" -
			nop				; Input         - "" -
			goto	WEO_#9			; Input         - "" -
			goto	WEO_#A			; Input         - "" -
WEO_#9			movf	EXP_IO_TMP,W		; Input          EXP_IO_IN_BYTE_1
			movwf	EXP_IO_IN_BYTE_1	; Input             - "" -
			goto	WEO_#D			; Input             - "" -
WEO_#A			movf	EXP_IO_TMP,W		; Input          EXP_IO_IN_BYTE_2
			movwf	EXP_IO_IN_BYTE_2	; Input             - "" -

WEO_#D			decfsz	EXP_IO_BYTE_COUNT,f	; Common I/O  Decrement and check EXP_IO_OUT_BYTE_COUNT state...
			goto	WEO			; Common I/O      THEN Return to main programme loop if NZ
							;                 ELSE Initiate latch sequence before Return if Z...
			retlw	H'0000'			; Common I/O        - "" -