PORT LIST           Release 47      Last Change: 8/13/95
[This file was provided by Wim Osterholt (2:512/56 or wim@djo.wtm.tudelft.nl).]

        XT, AT and PS/2  I/O port addresses

      Do NOT consider this information as complete and accurate.
      If you want to do hardware programming ALWAYS check the
      appropriate data sheets. Be aware that erroneously programming
      can put your hardware or your data at risk. 

      There are a few memory mapped addresses in use for I/O functions which
      are listed at the end of this file; see MEMORY.LST for memory-mapped
      I/O accessible from real mode.

---------------------------------------------
 New Format:

PPPPw RW  description

where:  PPPP    is the four-digit hex port number
    w   is blank for byte-size port, 'w' for word, and 'd' for dword
    R   is blank if not readable, 'r' if sometimes readable, 'R' if
        "always" readable, '?' if readability unknown
    W   is blank if not writable, 'w' if sometimes writable, 'W' if
        "always" writable, '?' if writability unknown
[Note: I have not yet completed the format conversion; the heading lines
 will be changed to a form similar to that used by the main list in INTER48:
PORT 0000-001F - DMA 1 - FIRST DIRECT MEMORY ACCESS CONTROLLER (8237)
 and
PORT 0018 - PS/2 - EXTENDED FUNCTION REGISTER]

---------------------------------------------
03F8-03FF ----  serial port (8250,8250A,8251,16450,16550,16550A,etc.) COM1
        same as 02E8, 02F8 and 03E8

         chips overview:
         8250  original PC, specified up to 56Kbd, but mostly runs
               only 9600Bd, no scratchregister, bug: sometimes shots
               ints without reasons
         8250A, 16450, 16C451: ATs, most chips run up to 115KBd,
               no bug: shots no causeless ints
         8250B: PC,XT,AT, pseudo bug: shots one causeless int for
            compatibility with 8250, runs up to 56KBd
         16550, 16550N, 16550V: early PS/2, FIFO bugs
         16550A,16550AF,16550AFN,16550C,16C551,16C552: PS/2, FIFO ok
         82510: laptops & industry, multi emulation mode
            (default=16450), special-FIFO.
         8251: completely different synchronous SIO chip, not
            compatible!

03F8   W  serial port, transmitter holding register (THR), which contains the
      character to be sent. Bit 0 is sent first.
        bit 7-0   data bits when DLAB=0 (Divisor Latch Access Bit)
03F8  R   receiver buffer register (RBR), which contains the received
      character. Bit 0 is received first
         bit 7-0   data bits when DLAB=0 (Divisor Latch Access Bit)
03F8  RW  divisor latch low byte (DLL) when DLAB=1

03F9  RW  divisor latch high byte (DLM) when DLAB=1
          some baudrates (using standard 1.8432 Mhz clock)
               baudrate    divisor   DLM  DLL
                50     2304       09h 00h
                75     1536       06h 00h
               110     1047       04h 17h
               134,5    857       03h 59h
               150      768       03h 00h
               300      384       01h 80h
               600      192       00h C0h
              1200       96       00h 60h
              1800       64       00h 40h
              2000       58       00h 3Ah
              2400       48       00h 30h
              3600       32       00h 20h
              4800       24       00h 18h
              7200       16       00h 10h
              9600       12       00h 0Ch
             19200        6       00h 06h
             38400        3       00h 03h
             57600        2       00h 02h
            115200        1       00h 01h

         MIDI baudrate 32250Bd with 4Mhz quarz for c't MIDI interface
         following c't 01/1991
            '14400'           00h 08h

03F9  RW  interrupt enable register (IER) when DLAB=0
         bits 7-4   reserved (0)
         bit 3 = 1  modem-status interrupt enable
         bit 2 = 1  receiver-line-status interrupt enable
         bit 1 = 1  transmitter-holding-register empty interrupt enable
         bit 0 = 1  received-data-available interrupt enable
                (also 16550(A) timeout interrupt)

          - 16550(A) will interrupt with a timeout if data exists in the
        FIFO and isn't read within the time it takes to receive four
        bytes or if no data is received within the time it takes to
        receive four bytes

03FA  R   interrupt identification register. Information about a pending
        interrupt is stored here. When the ID register is addressed,
        the highest priority interrupt is held, and no other interrupts
        are acknowledged until the CPU services that interrupt.
         bit 7-6 = 00  reserved on 8250, 8251, 16450
             = 01  if FIFO queues enabled but unusable (16550 only)
             = 11  if FIFO queues are enabled (16550A only)
         bit 5-4 = 0 reserved
         bit 3   = 0 reserved  8250, 16450
             = 1 16550  timeout int. pending
         bit 2-1 identify pending interrupt with the highest priority
          = 11  receiver line status interrupt. priority=highest
          = 10  received data available register interrupt. pr.=second
          = 01  transmitter holding register empty interrupt. pr.=third
          = 00  modem status interrupt. priority=fourth
         bit 0 = 0  interrupt pending. contents of register can be used
                as a pointer to the appropriate int.service routine
             1  no interrupt pending

          - interrupt pending flag uses reverse logic, 0=pending, 1=none
          - interrupt will occur if any of the line status bits are set
          - THRE bit is set when THRE register is emptied into the TSR

03FA   W  16650 FIFO Control Register (FCR)
         bit 7-6 = received data available interrupt trigger level
            00  1 byte
            01  4 bytes
            10  8 bytes
            11 14 bytes
         bit 5-4 = 00 reserved
         bit 3   = 1  change RXRDY  TXRDY pins from mode 0 to mode 1
         bit 2   = 1  clear XMIT FIFO
         bit 1   = 1  clear RCVR FIFO
         bit 0   = 1  enable clear XMIT and RCVR FIFO queues

          - bit 0 must be set in order to write to other FCR bits
          - bit 1 when set  the RCVR FIFO is cleared and this bit is reset
         the receiver shift register is not cleared
          - bit 2 when set  the XMIT FIFO is cleared and this bit is reset
         the transmit shift register is not cleared
          - due to a hardware bug, 16550 FIFOs don't work correctly (this
        was fixed in the 16550A)
03FB  RW  line control register (LCR)
         bit 7 = 1  divisor latch access bit (DLAB)
             0  receiver buffer, transmitter holding, or interrupt
                enable register access
         bit 6 = 1  set break enable. serial ouput is forced to spacing
                state and remains there.
         bit 5-3 =  PM2 PM1 PM0
                 x   x   0   = no parity
                 0   0   1   = odd parity
                 0   1   1   = even parity
                 1   0   1   = high parity (sticky)
                 1   1   1   = low parity (sticky)
                 x   x   1   = software parity
         bit 2 = stop bit length (STB/SBL)
             0  one stop bit 
             1  2 stop bits with (word length 6, 7, 8)
                1.5 stop bits with word length 5
         bit 1-0 (WLS1-0, CL1-0)
             00 word length is 5 bits
             01 word length is 6 bits
             10 word length is 7 bits
             11 word length is 8 bits
03FC  RW  modem control register
         bit 7-5 = 0  reserved
         bit 4 = 1  loopback mode for diagnostic testing of serial port
                output of transmitter shift register is looped back
                to receiver shift register input. In this mode
                transmitted data is received immediately so that
                the CPU can verify the transmit data/receive data
                serial port paths.
                If OUT2 is disabled, there is no officially
                way to generate an IRQ during loopback mode.
         bit 3 = 1  auxiliary user-designated output 2 (OUT2)
                because of external circuity OUT2 must be 1 to
                master-intr-enableing. Bug: Some Toshiba Laptops
                utilize this bit vice versa, newer Toshiba machines
                allow to assign the bits polarity in system setup.
                82050: This bit is only effective, if the chip is
                being used with an externally generated clock.
         bit 2 = 1/0  auxiliary user-designated output 1 (OUT1)
                should generally be cleared!!
                Some external hardware, e.g. c't MIDI interface
                (and compatibles) uses this bit to change the 8250
                input clock from 1,8432 MHz to 4Mhz (enableing
                MIDI conform baudrates) and switching to MIDI
                compatible current loop connectors.
         bit 1 = 1  force request-to-send active (RTS)
         bit 0 = 1  force data-terminal-ready active (DTR)
03FD  R   line status register
         bit 7 = 0  reserved
               = 1  on some chips produced by UMC
         bit 6 = 1  transmitter shift and holding registers empty
         bit 5 = 1  transmitter holding register empty (THRE)
            Controller is ready to accept a new character to send.
         bit 4 = 1  break interrupt. the received data input is held in
                in the zero bit state longer than the time of start
                bit + data bits + parity bit + stop bits.
         bit 3 = 1  framing error (FE). the stop bit that follows the
                last parity or data bit is a zero bit.
         bit 2 = 1  parity error (PE). Character has wrong parity
         bit 1 = 1  overrun error (OE). a character was sent to the
                receiver buffer before the previous character in
                the buffer could be read. This destroys the
                previous character.
         bit 0 = 1  data ready. a complete incoming character has been
                received and sent to the receiver buffer register.
03FE  R   modem status register (MSR)
         bit 7 = 1  data carrier detect (-DCD)
         bit 6 = 1  ring indicator (-RI)
         bit 5 = 1  data set ready (-DSR)
         bit 4 = 1  clear to send (-CTS)
         bit 3 = 1  delta data carrier detect (DDCD)
         bit 2 = 1  trailing edge ring indicator (TERI)
         bit 1 = 1  delta data set ready (DDSR)
         bit 0 = 1  delta clear to send (DCTS)

          - bits 0-3 are reset when the CPU reads the MSR
          - bit 4 is the Modem Control Register RTS during loopback test
          - bit 5 is the Modem Control Register DTR during loopback test
          - bit 6 is the Modem Control Register OUT1 during loopback test
          - bit 7 is the Modem Control Register OUT2 during loopback test
03FF  RW  scratch register (SCR)
        (not used for serial I/O; available to any application using
        16450,16550) (not present on original 8250)
---------------------------------------------
02F8-02FF ----  serial port, same as 02E8, 03E8 and 03F8 (COM2)

02F8   W  transmitter holding register
02F8  R   receiver buffer register
02F8  RW  divisor latch, low byte   when DLAB=1
02F9  RW  divisor latch, high byte  when DLAB=1
02F9  RW  interrupt enable register when DLAB=0
02FA  R   interrupt identification register
02FB  RW  line control register
02FC  RW  modem control register
02FD  R   line status register
02FF  RW  scratch register
---------------------------------------------
03E8-03EF ----  serial port, same as 02E8, 02F8 and 03F8 (COM3)
SeeAlso: 03F8-03FF
---------------------------------------------
02E8-02EF ----  serial port, same as 02F8, 03E8 and 03F8 (COM4)
---------------------------------------------
03BC-03BF ----  PARALLEL PRINTER PORT (MDA's LPT1)
Range:  PORT 0278h, PORT 0378h, or PORT 03BCh

03BC   W  data port
03BC  R   bidirectional port: input from connector
          unidirectional port: last value written to port
03BD  RW  status port (see #P101)
03BE  RW  control port (see #P102)

Bitfields for parallel interface status port:
Bit(s)  Description (Table P101)
 7  busy
 6  NOT acknowledge (approx. 5us low pulse)
 5  out of paper
 4  printer is selected
 3  *no* error
 2  IRQ has *not* occurred
    (PS/2) printer returned -ACK
 1-0    reserved
SeeAlso: #P102

Bitfields for parallel interface control port:
Bit(s)  Description (Table P102)
 7-5    reserved
 7  (see PORT 037Bh bit 7)
 5  enable bidirectional port
    (PS/2 also requires enabling via port 0102h)
 4  enable IRQ (via -ACK)
 3  select printer (SLCT IN line)
 2  =0 initialize printer (-RESET line)
 1  automatic line feed
 0  strobe (must be set for minimum of 5 microseconds)
SeeAlso: #P101
---------------------------------------------
0378-037A ----  parallel printer port, same as 0278 and 03BC

0378   W  data port
0379  RW  status port
037A  RW  control port

037B  ??  bit 7: shadow RAM on/off (UniRAM adapter,according to c't 7/90)
---------------------------------------------
0278-027E ----  parallel printer port, same as 0378 and 03BC

0278   W  data port
0279  RW  status port
027A  RW  control port
---------------------------------------------
