--===========================================================================--
-- Design units : Scrambler (Entity and architecture)
--
-- File name    : scrambler.vhd
--
-- Purpose      : Scramble bit stream for G3RUH FSK modem
--
-- Note         : y=1+x^5+x^17
--
-- Limitations  : NON-COMMERCIAL USAGE ONLY
--
-- Errors       :
--
-- Library      :
--
--Dependencies  :
--
-- Author       : Juergen Hasch, hasch@t-online.de
--                Meisenstr. 23
--                73066 Uhingen
--                Germany
--
-- Synthesis    : Xilinx Foundation 1.4
-------------------------------------------------------------------------------
-- Revision list
-- Version Author Date       Changes
-- 1.0     JH     18 Dec 97  File created
--
--
-------------------------------------------------------------------------------

Library ieee;
Use ieee.std_logic_1164.all;


entity scrambler is
  port(
    datain:  in  std_logic;                       -- input bit
    clock:    in  std_logic;                       -- data shift clock
    dataout: out std_logic_vector(7 downto 0));  -- scrambled output
end scrambler;

architecture behaviour of scrambler is
  signal shift_reg: std_logic_vector(16 downto 0);        -- shift register
begin
  process(clock,datain)
  begin
      if (clock'event and clock='1') then
        shift_reg(0) <= datain xor shift_reg(16);
        shift_reg(1) <= shift_reg(0);
        shift_reg(2) <= shift_reg(1);
        shift_reg(3) <= shift_reg(2);
        shift_reg(4) <= shift_reg(3);
        shift_reg(5) <= shift_reg(4) xor shift_reg(16);
        shift_reg(6) <= shift_reg(5);
        shift_reg(7) <= shift_reg(6);
        shift_reg(8) <= shift_reg(7);
        shift_reg(9) <= shift_reg(8);
        shift_reg(10) <= shift_reg(9);
        shift_reg(11) <= shift_reg(10);
        shift_reg(12) <= shift_reg(11);
        shift_reg(13) <= shift_reg(12);
        shift_reg(14) <= shift_reg(13);
        shift_reg(15) <= shift_reg(14);
        shift_reg(16) <= shift_reg(15);
      end if;
    end process;
  dataout <= shift_reg(16 downto 9);                     -- get 8 output bits
end behaviour;
--========================= End of Scrambler ================================--