--===========================================================================--
-- Design units : HDLC encoder (Entity and architecture)
--
-- File name    : hdlcenc.vhd
--
-- Purpose      : HDLC encoder (bitstuffing and flag generation)
--
-- Note         : NON-COMMERCIAL USAGE ONLY
--
-- Limitations  :
--
-- Errors       :
--
-- Library      :
--
-- Dependencies :
--
-- Author       : Juergen Hasch, hasch@t-online.de
--                Meisenstr. 23
--                73066 Uhingen
--                Germany
--
-- Synthesis    : Xilinx foundation F1.4
-------------------------------------------------------------------------------
-- Revision list
-- Version Author Date       Changes
-- 1.0     JH     28 Mar 98  File created
-- 1.1     JH     29 Mar 98  Stripped HDLC encoding, only raw data is output now
-- 1.2     JH     11 Apr 98  added ram access control
-- 
-------------------------------------------------------------------------------

Library ieee;
Use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.converters.all;

entity hdlc_enc is
  port(
    reset:    in  std_logic;
    din:      in  std_logic_vector(7 downto 0);     -- data input
    clock:    in  std_logic;                        -- bit clock
    clock2:   in  std_logic;                        -- master clock
    dataout:  out std_logic;                        -- data output
    empty:    in  std_logic;
    rdok:     in  std_logic;
    rdreq:    out std_logic);                      -- flag to get new data
end hdlc_enc;


architecture behaviour of hdlc_enc is
  signal counter: std_logic_vector(2 downto 0);
  signal shift_reg: std_logic_vector(7 downto 0);
  signal data: std_logic_vector(7 downto 0);
  signal clrreq: std_logic;
begin

--
-- request new data
--
process(reset,rdok,empty,clock,clrreq)
begin
  if (clrreq='1') then
    rdreq <= '0'; 
  elsif (clock'event and clock='1' ) then
    if (counter="110" and empty='0') then
      rdreq <= '1';
    end if;  
  end if;
end process;

--
-- clear data request
--
process(reset,rdok,empty,clock,clock2,counter)
begin
  if (counter="100") then
    clrreq <= '0'; 
  elsif (clock2'event and clock2='1' ) then
    if (rdok='1') then
      clrreq<='1';
      data <= din;
    end if;
  end if;
end process;
 
--
-- put data in shift register and shift out register
--
process(reset,clock,clock2,shift_reg,counter,rdok,din)
begin

  if (reset='1') then
    shift_reg <= (others => '0');
    dataout <='0';
  elsif (clock'event and clock='1') then
    dataout <= shift_reg(0); 
    if (counter = "111" ) then
      shift_reg <= data;
    else    
      shift_reg(0) <= shift_reg(1);
      shift_reg(1) <= shift_reg(2);
      shift_reg(2) <= shift_reg(3);
      shift_reg(3) <= shift_reg(4);
      shift_reg(4) <= shift_reg(5);
      shift_reg(5) <= shift_reg(6);
      shift_reg(6) <= shift_reg(7);
      shift_reg(7) <= shift_reg(0);
    end if;
  end if;
end process;

--
-- tx bit counter
--
process(reset,counter,clock)
  begin
  if (reset='1') then
      counter <= "000";
  elsif (clock'event and clock='1') then
    counter <=counter+1;
  end if;
end process;

end behaviour;
--========================= End of rxctrl ================================--