--===========================================================================--
-- Design units : FIR filtering (entity and architecutre)
--
-- File name    : firfilt.vhd
--
-- Purpose      : Finite impulse filter for transmission pulse shaping
--                8 taps with 4 times oversampling
--                symmetrical impulse response
-- Note         : NON-COMMERCIAL USAGE ONLY
--
-- Limitations  :
--
-- Errors       :
--
-- Library      :
--
-- Dependencies :
--
-- Author       : Juergen Hasch, hasch@t-online.de
--                Meisenstr. 23
--                73066 Uhingen
--                Germany
--
-- Synthesis    : Xilinx Foundation F1.4
-------------------------------------------------------------------------------
-- Revision list
-- Version Author Date       Changes
-- 1.0     JH     14 Mar 98  File created
-- 1.1     JH     03 Oct 98  Adjusted to spartan 
--
-------------------------------------------------------------------------------

Library ieee;
Use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.converters.all;

entity firfilt is
    port (
      clk4:     in  std_logic;                      -- 4 times bit clock
      clk2:     in  std_logic;                      -- 2 times bit clock
      clk:      in  std_logic;                      -- bit clock
      din:      in  std_logic_vector(7 downto 0);   -- input data stream, clocked at rising edge 
      fout:     out std_logic_vector(7 downto 0));
end firfilt;
architecture behavior of firfilt is

type C_ARR1 is array ( 0 to 15) of integer range 0 to 31;
type C_ARR2 is array ( 0 to 15) of integer range 0 to 255;
 
--
-- filter coefficients with raised consine shape
-- alpha=0.35
-- four times oversampling with 8 taps
--
constant COEFF_0a: C_ARR1 := ( 6, 6, 5, 4, 8, 8, 7, 6, 11, 11, 9, 9, 13, 13, 12, 11);
constant COEFF_0b: C_ARR1 := ( 6, 5, 4, 2, 13, 11, 10, 9, 15, 14, 13, 11, 22, 20, 20, 18);
constant COEFF_1a: C_ARR2 := ( 50, 44, 36, 30, 69, 63, 55, 49, 196, 190, 182, 176, 215, 209, 201, 195);
constant COEFF_1b: C_ARR2 := ( 50, 30, 24, 5, 117, 98, 92, 72, 166, 146, 140, 120, 233, 213, 208, 188);

signal swap0: std_logic_vector(3 downto 0);   -- data bits 0,1,6,7
signal swap1: std_logic_vector(3 downto 0);   -- data bits 2,3,4,5
signal sel_lut: std_logic;                    -- select coefficient table
begin

--
-- calculate filter output 
--
process(clk4,sel_lut)
begin
  if (clk4='1' and clk4'event) then  
    if ( sel_lut ='0') then
      fout <= CONV5(COEFF_0a( CONV(swap0))) + CONV8(COEFF_1a( CONV(swap1)));  
    else
      fout <= CONV5(COEFF_0b( CONV(swap0))) + CONV8(COEFF_1b( CONV(swap1)));  
    end if;
  end if;
end process;
  
--
-- data swapper
--
process(clk,clk2,clk4,din)
  variable sel : std_logic_vector(1 downto 0);
begin
  if (clk4 = '1' and clk4'event) then
    sel := ( clk2 & clk );
    case ( sel ) is
      when "01" =>
        swap0 <= ( din(6) & din(1) & din(7) & din(0) );
        swap1 <= ( din(4) & din(3) & din(5) & din(2) );
        sel_lut <= '0';
      when "11" =>
        swap0 <= ( din(6) & din(1) & din(7) & din(0) );
        swap1 <= ( din(4) & din(3) & din(5) & din(2) );
        sel_lut <= '1';
      when "00" =>
        swap0 <= ( din(1) & din(6) & din(0) & din(7) );
        swap1 <= ( din(3) & din(4) & din(2) & din(5) );
        sel_lut <= '1';
      when "10" =>
        swap0 <= ( din(1) & din(6) & din(0) & din(7) );
        swap1 <= ( din(3) & din(4) & din(2) & din(5) );
        sel_lut <= '0';
    end case;
  end if;
end process;

end behavior;
--========================== End of firfilt =================================--