--===========================================================================--
-- Design units : EPP CONTROLLER (entity and architecutre)
--
-- File name    : eppctrl.vhd
--
-- Purpose      : EPP interface controller
--
-- Note         : NON-COMMERCIAL USAGE ONLY
--
-- Limitations  :
--
-- Errors       :
--
-- Library      :
--
-- Dependencies :
--
-- Author       : Juergen Hasch, hasch@t-online.de
--                Meisenstr. 23
--                73066 Uhingen
--                Germany
--
-- Synthesis    : Xilinx Foundation 1.4
-------------------------------------------------------------------------------
-- Revision list
-- Version Author Date       Changes
-- 1.0     JH     28 Mar 98  File created
-- 1.1     JH     21 May 98  moved address generation to ramacc
-- 1.1a    JH     03 Oct 98  some cleanup
--
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.converters.all;

entity eppctrl is
  port(
      clk:        in     std_logic;                     -- master clock
      write:      in     std_logic;                     -- epp read/write
      eppin:      in     STD_LOGIC_VECTOR (7 downto 0); --
      eppout:     out    STD_LOGIC_VECTOR (7 downto 0); --
      enable:     out    STD_LOGIC;                     --
      datastr:    in     std_logic;                     -- epp data strobe
      addrstr:    in     std_logic;                     -- epp address strobe
      datain:     in     std_logic_vector(7 downto 0);  -- data bus to epp
      dataout:    out    STD_LOGIC_VECTOR (7 downto 0); --
      wrreq:      out    std_logic;                     -- epp write request
      ok:         in     std_logic;                     -- epp write request finished
      rdreq:      out    std_logic;                     -- epp read request
      txbufempty: in     std_logic;                     -- tx buffer empty flag
      rxframeavl: in     std_logic;                     -- rx frame in ram available
      dcd:        in     std_logic;                     -- dcd from receiver
      con:        buffer std_logic;                     -- con led
      sta:        buffer std_logic;                     -- sta led
      ptt:        buffer std_logic;                     -- ptt
      eppwait:    out    std_logic;                     -- wait signal to epp
      eppint:     out    std_logic);                    -- interrupt signal to epp
  end eppctrl;    

architecture behavior of eppctrl is
  signal rx_int_enable : std_logic;                     -- receive interrupt enable
  signal tx_int_enable : std_logic;                     -- transmit interrupt enable
  
  signal pre_req : std_logic;                           -- datastr clocked in to falling edge of clk
  signal data_wait : std_logic;                         -- wait signal for epp
  signal finished : std_logic;  
begin
dataout<= eppin;     -- epp write data gets through directly
eppwait <= finished; -- set epp wait pin

--
-- interrupt generation
--  generate interrupt when tx buffer is empty or a complete frame from
--  receiver is availavle
--
p1: process(txbufempty,rxframeavl,rx_int_enable,tx_int_enable)
begin
 if ((txbufempty='1' and tx_int_enable='1') or (rxframeavl='1' and rx_int_enable='1')) then
    eppint <='1';
 else
    eppint <='0';
 end if;
end process;

--
-- set finished flag when ram controller tells us transfer has been completed
-- ( immediately for addrstr)
--
pp: process(clk,ok,datastr,addrstr)
begin
  if (clk='1' and clk'event) then
    if (ok='1' or ( addrstr='0' and pre_req='1')) then
      finished <='1';
    else
      finished <='0';
    end if;
  end if;
end process;

--
-- set epp data output
--
p4: process(clk,datastr,datain,addrstr,rx_int_enable,tx_int_enable,dcd,
        rxframeavl,txbufempty,datain,ptt,con,sta)
  begin
  if (clk='1' and clk'event) then
    if (addrstr='0') then
      eppout(0) <= '-'; --rx_int_enable;        -- read status command
      eppout(1) <= '-'; --tx_int_enable;
      eppout(2) <= '-'; --con;
      eppout(3) <= '-'; --sta;
      eppout(4) <= '-'; --ptt;
      eppout(5) <= dcd;
      eppout(6) <= rxframeavl;
      eppout(7) <= txbufempty;
    else
      eppout <= datain;
    end if;
  end if;  
end process;

--
-- set data direction
--
p5: process(write,datastr,addrstr)
begin
  if (datastr='0' or addrstr='0') then    -- epp data read cycle: output data
    enable<=not(write);
  else                                    -- epp write cycle: high impedance
    enable<='1';                          -- datastr and addrstr;
  end if;
end process;

--
-- synchronize datastr to master clock
-- clock in datastr with two following ff's to avaid metastability
--
p6: process(clk,ok,datastr)
begin
  if (clk='0' and clk'event ) then
    if (datastr='1' and addrstr='1') then
      pre_req <= '0';
    else
      pre_req <= '1';
    end if;  
  end if;
end process;

--
--
--  
p7: process(clk,finished,datastr)
begin
  if (datastr='1') then                                -- clear request immediately
    wrreq<='0';
    rdreq<='0';
  elsif (clk='0' and clk'event ) then
    wrreq <= pre_req and not(write) and not(finished); -- epp write request (memory write)
    rdreq <= pre_req and write and not(finished);      -- epp read request (memory read)
  end if;
end process;
 
--
-- address read action
--
process(clk,addrstr,eppin,write)
  begin
  if (clk='1' and clk'event) then
    if (addrstr='0' and write='0') then 
      rx_int_enable <= eppin(0);
      tx_int_enable <= eppin(1);
      con           <= eppin(2);
      sta           <= eppin(3);
      ptt           <= eppin(4);
    end if;
  end if;
end process;

end behavior;
--============================ End of eppctrl ===================================--