--===========================================================================--
-- Design units : clock divider (Entity and architecture)
--
-- File name    : clockdiv.vhd ** BITCLK4 ist BITCLK8 **
--
-- Purpose      : divide clock by 64
--
-- Note         : NON-COMMERCIAL USAGE ONLY
--
-- Limitations  :
--
-- Errors       :
--
-- Library      :
--
-- Dependencies :
--
-- Author       : Juergen Hasch, hasch@t-online.de
--                Meisenstr. 23
--                73066 Uhingen
--                Germany
--
-- Synthesis    : Xilinx Foundation 1.4
-------------------------------------------------------------------------------
-- Revision list
-- Version Author Date       Changes
-- 1.0     JH     14 Mar 98  File created
--
--
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity clockdiv is
  port(
    clock:       in   std_logic;         -- clock input
    bitclk4:     out  std_logic;         -- clock/16 (4*bit clock)
    bitclk2:     out  std_logic;         -- clock/32 (2*bit clock)
    bitclk:      out  std_logic);        -- clock/64 (bit clock)
end clockdiv;

architecture BEHAVIOUR of clockdiv is
  signal q: std_logic_vector(5 downto 0);
begin

process(clock,q)
  begin
  if (clock='1' and clock'event) then
    q <= q+1;
  end if;
  bitclk4 <= q(3);
  bitclk2 <= q(4);
  bitclk  <= q(5); 
end process;

end BEHAVIOUR;
--============================ End of clockdiv ===================================--