File: C:\pic\dsPIC33EP_Si5351_Synth\Documentation\Si5351_Frequency_Modulation.txt
Copy: C:\Elektronik_Projekte\Si5351_Clock_Generator\Documentation\Si5351_Frequency_Modulation.txt
Date: 2021-10-31
Author: Wolfgang Buescher, DL4YHF.

   To be calculated by DL4YHF's "CalcEd" (a complex calulating text editor) !


@format("%lf")  // decimal output format for DL4YHF's "CalcEd"

Introduction
-------------

This document describes a principle of FREQUENCY MODULATING an Si5351 frequency synthesizer
via software. It does NOT use an Si5351B (which can emulate a true VCXO, voltage-controlled
crystal oscillator) simply because in 2021, eval-boards with an Si5351B were unobtainable.

If the 'audio quality' generated by rapidly reprogramming an Si5351A via I2C-bus would be
good enough for a narrow-band FM repeater can only be found out by experimentation.
Initial tests showed a dependence between FREQUENCY OFFSET and "reprogramming rate";
see measurements further down ("Si5351A output frequency depends on the UPDATE RATE..?").



I2C bus limitations / maximum sampling rate for the modulator signal
---------------------------------------------------------------------


After getting close to the maximum I2C bit clock supported by master (dsPIC33)
and slave (Si5351A), the maximum 'sampling rate' for the frequency-modulating
signal was around 16 to 18 kHz, with 4 bytes per I2C frame sent to the Si5351.
  (details in dsPIC33EP_Si5351_Synth/dsPIC33EPxx_Drivers/i2c_dsPIC33EP.c ,
          I2C_Init(), using I2C_BRG = 63 ('BaudRateGenerator') at Fcy=60 MHz)

With only two adjacent registers in the Si5351 reprogrammed per sample,
the achieveable deviation was limited, and (since it was impossible to invoke
the Farey algorithm, and reprogram the entire 'PLL Feedback Fractional Multisynth'
for each audio sample) on 1298 MHz (9 * 144.22x MHz), the frequency steps
will be coarse.
One of the main problems was the strange architecture of the Si5351's bitgroups
'P1', 'P2', 'P3' : The fractional multiplier (for the PLL feedback)..

   ;   F_vco :=  F_ref * (a + b/c) 

... must be converted into 'P1', 'P2', and 'P3' as described in 619 page 3 :

   // > The fractional ratio        a + b/c
   // > has a valid range of 15 + 0/1,048,575 and 90 
   // > and is represented in the Si5351 register space 
   // > using the equations below.
   // > MSNx_P1[bits 17..0] = 128 * a + Floor( 128 * b/c ) - 512
   // > MSNx_P2[bits 19..0] = 128 * b - c * Floor( 128 * b/c )
   // > MSNx_P3[bits 19..0] = c

That's a dilemma for "fast frequency modulation", because ...
 * modifying the numerator 'b' not only affects 'P2' but also 'P1',
   unless b < c/128 (which causes the "strange Floor-term" to disappear).

 * modifying the denominator 'c' not only affects 'P3' but also
   'P1' and 'P2' ! 

 * modifying the integer part 'a' is useless for frequency modulation,
   much too coarse steps for narrow-band FM.

Thus, for a start, only the least significant 16 bits of the 20-bit
numerator 'b' were reprogrammed about 16000 times per second,
by writing to what the strange datasheet called
     "Register 32. Multisynth NA Parameter 2"
     (bits 15..8 of the PLLA Feedback Divider's 20-bit numerator)
 and "Register 33. Multisynth NA Parameter 2" 
     (bits 7..0 of the PLLA Feedback Divider's 20-bit numerator)



Si5351A output frequency depends on the UPDATE RATE of the 'PLL feedback' registers ?!
--------------------------------------------------------------------------------------

For reasons yet to be discovered, the output frequency depends
on the CALLING FREQUENCY (update rate) of Si5351_SendFMSample().
Some initial measurements (firmware date 2021-08-24) :
  TX frequency   = 144.222 222 21 MHz
  Reference freq =  25.000 000 00 MHz (from a good 'analog' TCXO)
  Modulation:  "Manual / Param 1"
  Output measured on the 9-th harmonic; near 1298 MHz,
  using a "calibrated" IC-9700 in CW.
  Update rate of 'P2' bits 15..0 (= calls of Si5351_SendFMSample() per second)
   = ca. 15.8 kHz (measured on the I2C bus with an o-scope) .

  Parameter 1     | f_out with      | f_out with      | delta f_out
      (FM sample) | dsPIC running   | dsPIC paused    | running/paused
  ----------------+-----------------+-----------------+---------------
         0        | 1297.993314 MHz | 1297.993328 MHz | 14 Hz
       1...267    | almost as above |                 |
        267       | 1297.993322 MHz | 1297.993409 MHz | 87 Hz
        268       | 1297.993336 MHz,| 1297.993406 MHz,| 70 Hz
                  |  audible wobble |     no wobbling | 
     269...277    | almost as above |                 |
        278       | 1297.993388 MHz,| 1297.993412 MHz,| 24 Hz
                  |  audible wobble |     no wobbling | 
     279...287    | almost as above |                 |
        288       | 1297.993411 MHz,| 1297.993414 MHz,|  3 Hz
                  |     no wobbling |     no wobbling |
     289...589    | almost as above |                 | 
        589       | 1297.993414 MHz,| 1297.993505 MHz,| 91 Hz
                  |     no wobbling |     no wobbling |
        590       | 1297.993428 MHz,| 1297.993507 MHz,| 79 Hz
                  |  audible wobble |     no wobbling | 
    For the next measurements, Parameter 1 was incremented
    until the next AUDIBLE step, keeping the dsPIC running.
    Values of Parameter 1 without an audible step aren't listed.
        600       | 1297.993464 MHz |                 |
        610       | 1297.993508 MHz |                 |
        922       | 1297.993556 MHz | 1297.993611 MHz | 55 Hz
        932       | 1297.993610 MHz | 1297.993615 MHz |  5 Hz
       1244       | 1297.993648 MHz | 1297.993704 MHz | 56 Hz



Required stepwidth (resolution) of the modulated RF carrier, deviation, bandwidth
-----------------------------------------------------------------------------------


For the planned 1298 MHz frequency modulator, it doesn't matter HOW MUCH
the output divider divides the VFO frequency - the ratio of the frequency deviation,
divided by the center frequency, remains the same because the Si5351's output
signal will be MULTIPLIED UP (not "mixed up" with a constant UHF carrier).

Assume a frequency deviation of +/- 5 kHz on the UHF carrier, e.g. the instantaneous
carrier may swing from 1298 MHz - 5 kHz to 1298 MHz + 5 kHz during the modulation
peaks, thus the Carson bandwidth when modulated with a 3 kHz audio signal would be:

     CBW = 2 * (f_dev + f_mod), where:
               f_dev = peak frequency deviation
               f_mod = modulation frequency

f_dev := 5kHz  =: 5000.000000
f_mod := 3kHz  =: 3000.000000
CBW   := 2*(f_dev+f_mod)  =: 16000.000000
  
Carson's rule says that 98% of the transmitter falls within the above bandwidth.
With repeaters spaced 25 kHz (as common in the 23 cm band), that's just ok, but:

 (from www.repeater-builder.com/tech-info/modulation-spectrum/modulation-spectrum.html)

 > Theoretically an FM signal has an infinite number of sidebands and hence
 > an infinite bandwidth, but in practice all significant sideband energy (98% or more)
 > is concentrated within the bandwidth defined by Carson's Rule. 
 > This is equivalent to everything less than 20dB below the carrier level. 
 > The remaining transmitted sidebands, however low they may be, can still 
 > wreak havoc with nearby receivers.

So, in this case, the ratio of FM deviation to carrier frequency shall be:

dev_rel := 5kHz / 1298MHz  =: 0.000004

With the Si5351's INTERNAL VCO frequency near 900 MHz, the maximum deviation
(to "one side" of the carrier) generated by the digital FM audio samples
would have to be 

900MHz * dev_rel   =: 3466.872111

If (as used at DB0BI at the time of this writing), the transmitter itself
multiplies the output from the Si5351 by 128 (PLL with simple binary divider),
thus the synthesizer's output frequency would be APPROXIMATELY..

f_out_radio := 1298MHz
f_out_synth := f_out_radio / 128  =: 10140625.000000

..and absolute the maximum FM deviation in Hertz:
f_out_synth * dev_rel   =: 39.062500

 ( 10.14 MHz carrier +/- 39 Hz deviation, ideally in 4096 steps 
   from a 12-bit A/D converter.. THAT'S TOUGH ! )


Where to inject the modulation .. PLL feedback or fractional OUTPUT divider ?
=============================================================================


Frequency modulation via the PLL *feedback* multisynth (fractional divider)
---------------------------------------------------------------------------

For an initial test, the modulator signal was injected into the lower
16 bits of the PLL feedback "multisynth", i.e. into the lower 16 bits
of numerator 'a' in the following formula for the Si5351's INTERNAL VCO:

 Produce the FREQUENCY MODULATION at the highest possible *VCO* frequency 
 (<= 900 MHz), and use a *FRACTIONAL* output divider to achieve the precise
 output frequency (more on that later). Theoretic example:

 ;     f_vco :=  f_ref * (a + b/c) 

f_ref := 25MHz
a := 35          ; integer part for the highest allowed internal VCO frequency
b := 32767       ; numerator for the "center frequency" (16 bit FM samples)
c := 1048575     ; highest possible denominator of "feedback multisynth" (2^20-1)
f_vco_center :=  f_ref * (a + b/c)   =: 875781226.903178

VCO frequencies with FM samples '+1' and '-1' (one step above and below "zero"):
f_vco_p1  :=  f_ref * (a + (b+1)/c)   =: 875781250.745059
f_vco_m1  :=  f_ref * (a + (b-1)/c)   =: 875781203.061297

Frequency Modulator stepwidth for signals near 875 MHz :
delta_p1 := f_vco_p1-f_vco_center  =: 23.841881
delta_m1 := f_vco_m1-f_vco_center  =: -23.841881

"Scaled" into the 23 cm FM repeater band (1298 MHz), the FM-sample-stepwidth
would theoretically be 35 Hz, quite coarse..:
delta_p1 * 1298 / 875  =: 35.367727
 

For FM, only the lower 16 bits of numerator 'a' will be reprogrammed,
so we could keep the UPPER four bits of the numerator SET, e.g.
a = 0xFF0000 + 'FM samples' ranging from 0 to 65535 (center=32737):
b := 0x0F7FFF  =: 1015807.000000
c := 0x0FFFFF  =: 1048575.000000
f_vco_center :=  f_ref * (a + b/c)  =: 899218749.254941
New Frequency Modulator stepwidth for signals near 900 MHz :
f_vco_p1  :=  f_ref * (a + (b+1)/c) =: 899218773.096822
delta_p1 := f_vco_p1-f_vco_center   =: 23.841881
FM stepwidth "scaled" into the 23 cm FM repeater band (1298 MHz):
delta_p1 * 1298 / 900  =: 34.385290

Not much better, and not worth the effort. How to achieve 'finer steps', maybe using
the OUTPUT DIVIDER state (in the Si5351's fractional OUTPUT DIVIDER mode) ? 


Frequency modulation via the fractional OUTPUT divider ("Output Multisynth")
----------------------------------------------------------------------------


AN619, page 6, "4.1 Output Multisynth Settings (Synthesis Stage 2)" says:

 > Once the PLL source for the output Multisynth is selected,
 > the divide ratio can be set using the equations below.
 > Divider represented as a fractional number,
 >                a + b/c 
 > between 8+1/1048575 and 2048 .

(Very similar to the FEEDBACK multisynth, but here, a+b/c is a DIVIDER.
 All seem to be 20-bit values again, even though AN619 doesn't clearly state that.)



From AN691 page 2: The relationship between the VCO and output frequencies
is given below:
       f_out_synth = f_vco / ( Output_Multisynth * Rx )
          (ignore Rx here, it's an extra int divider for very low frequencies)
   Here: "Output_Multisynth" = a + b / c = output_divider .


FIRST test ... inject modulation into 16 LSbits of the NUMERATOR (b) :
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
f_out_radio := 1298MHz             =: 1298000000.000000
f_vco := 900MHz                    =: 900000000.000000
f_out_synth := 40.5625MHz          =: 40562500.000000
output_div := f_vco / f_out_synth  =: 22.187982
a := int( output_div )             =: 22.000000
;b := 0x0B7FFF ; numerator for the "center frequency" (16 bit FM samples); ok for f_out_synth = 10.14 MHz
;b := 0x007FFF ; useless; gives a stepwith of 338 Hz near 1298 MHz carrier.
;b := 0x037FFF ; numerator for the "center frequency" (16 bit FM samples); ok for f_out_synth = 144 MHz
b := 0x027FFF ; numerator for the "center frequency" (16 bit FM samples); ok for f_out_synth = 144 MHz
   output_div = a + b/c   -> resolve for c..
   -> (output_div-a) = b/c
   -> c = b/(output_div-a) :
c := int(b/(output_div-a))  =: 871569.000000
   b and c must be less than 2^20 (if it's not, reduce b):
b / 2^20  =: 0.156249
c / 2^20  =: 0.831193

f_out_synth_center := f_vco / (a + b/c)        =: 40562499.699432
f_out_synth_p1     := f_vco / (a + (b+1)/c)    =: 40562497.601916
f_out_synth_m1     := f_vco / (a + (b-1)/c)    =: 40562501.796947
Frequency Modulator stepwidth in Hertz near the above (low) synth output frequency :
delta_p1 := f_out_synth_p1-f_out_synth_center  =: -2.097515
delta_m1 := f_out_synth_m1-f_out_synth_center  =: 2.097515


Frequency Modulator stepwidth in Hertz near the final RF carrier frequency:
delta_p1 * (f_out_radio/f_out_synth)   =: -67.120486
f_out_radio =: 1298000000.000000
f_out_synth =: 40562500.000000
  (why is this resolution much better than when modulating the PLL FEEDBACK ?)


Test at 'maximum deviation', when fed with sample from a 12-bit A/D converter:
f_out_synth_p2047  := f_vco / (a + (b+2047)/c) =: 40558206.540050
f_out_synth_m2047  := f_vco / (a + (b-2047)/c) =: 40566793.767787
delta_p2047 := f_out_synth_p2047-f_out_synth_center  =: -4293.159382
delta_m2047 := f_out_synth_m2047-f_out_synth_center  =: 4294.068356
  (note the slight nonlinearity, but neglectable because a is much larger than b/c)


The above CalcEd code fragment was repeated for different SYNTHESISER OUTPUT frequencies,
but all multiplied by 2^N to the same f_out_radio. Results when modulating b:
     f_out_synth = 10.14MHz ->  14.7 Hz per LSBit at f_out_radio = 1298 MHz
     f_out_synth = 40.56MHz ->  67.1 Hz per LSBit at f_out_radio = 1298 MHz
     f_out_synth = 144MHz   -> 226.3 Hz per LSBit at f_out_radio = 1298 MHz




SECOND test ... inject modulation into 16 LSbits of the DENOMINATOR (c) :
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

  // (later copied into C:\pic\dsPIC33EP_Si5351_Synth\si5351.c) 
  // 
  // > f_out = f_vco / ( ( a   +   b  /    c ) * r_div )    [equation A]
  //            |          |       |       |         |
  //     ,------'  ,-------'       |       |         Additional divider for low
  //     |         |               |       |         frequenies, usually r_div=1
  //     |         |         ______|______  \____________
  //     Circa(!)  integer  |numerator,   | |denominator,|
  //     900 Mhz   part,    |20 bit,      | |20 bit,     |
  //               8..2047  |here:        | |here:       |
  //                        |controls the | |injects the |
  //                        |FM DEVIATION.| | MODULATION.|
  //                        '-------------' '------------'
  // Equation A results in a non-linear relation between c_out (with the
  // modulation in the lower bits), i.e. :
  //   c_out [20 bit] = c_const [4 bit] + c_mod[16 bit] .
  // The larger c_const, the more LINEAR the relation between c_mod and delta f_out.
  // 
  // Inputs (as later implemented in Si5351_GetOutputDividerParamsForFM()) :
f_vco     := 900MHz             =: 900000000.000000
f_out     := 1298.350MHz / 128  =: 10143359.375000
deviation := 4000Hz      / 128  =: 31.250000
c_center  := 0x0F7FFF           =: 1015807.000000
c_max     := 0x0FFFFF           =: 1048575.000000
c_min     := 0x0F0000           =: 983040.000000
@r_div  := 1 // our f_out is larger than 500 kHz; no need for the 'R divider' here


  We can already guesstimate a, because b/c is less than ONE,
  and a (the integer part) is much larger than one (remember, f_out << f_vco):
a := int(f_vco / f_out)   =: 88.000000

  For a start, throw the dice with a reasonable 'b' and calculate 
  the resulting frequency deviation. Don't twist your brain trying to solve
  the combined equation below for 'b_max' from a given deviation (it's quadratic):

                    f_vco                  f_vco
    deviation = ---------------  -  ---------------------
                (a+b/c_max) * R       (a+b/c_center) * R


  At this early stage, the center frequency doesn't need to be precise
              (we'll care for this later by SLIGHTLY adjusting f_vco).
b := 1000; for simplicity, start with an almost arbitrary value:
f_out_center := f_vco / ( ( a + b / c_center ) * r_div )  =: 10227158.318031
f_out_max    := f_vco / ( ( a + b / c_max )    * r_div )  =: 10227161.893285
delta_f := f_out_max - f_out_center  =: 3.575253
b := int(b * (deviation / delta_f))  =: 8740.000000
  Try one more iteration. b shouldn't change much now:
f_out_center := f_vco / ( ( a + b / c_center ) * r_div )  =: 10226272.877076
f_out_max    := f_vco / ( ( a + b / c_max )    * r_div )  =: 10226304.119465
delta_f := f_out_max - f_out_center  =: 31.242389
b := int(b * (deviation / delta_f))  =: 8742.000000
  b/c_min must be less than 1.0 : 
b/c_min   =: 0.008893

  Revise f_vco (in the firmware, using the fractional PLL FEEDBACK) :
f_vco := f_vco * (f_out/f_out_center)  =: 892702898.429832
  Double-check f_out_center; it should equal f_out now :
f_out_center := f_vco / ( a + b / c_center )  =: 10143359.148079

- - end of the FM example for 1298.350 MHz with 4000 Hz deviation - -





  For large FM deviation (relative to f_out), the upper 4 bits ALL SET 
  in the 20-bit denominator (c) may cause the numerator (b) exeed the 
  denominator. The Si5351's output frequency was erratic in such cases.
  See implementation of Si5351_GetOutputDividerParamsForFM() !
  Example:
  Test the same algorithm for much larger FM deviation : 
f_vco     := 900MHz      
;f_out    := 145.5MHz    // "CQ FM, CQ FM"... (impossible, 'a' gets too small for a FRACTIONAL output divider)
f_out     := 10.7MHz     // sigh.. so "modulate" an immediate frequency instead :o)
deviation := 5000;       // NBFM for the 2m band
; The following gave too large 'b' (b/c_min was 1.334 with this):
c_center  := 0x0F7FFF    =: 1015807.000000
c_max     := 0x0FFFFF    =: 1048575.000000
c_min     := 0x0F0000    =: 983040.000000
; 7 instead of 15 in the upper 4 bits of the denominator (c) should do the job,
;  if -with the above initial settings- b/c_min as LESS THAN TWO but MORE THAN ONE: 
c_center  := 0x077FFF    =: 491519.000000
c_max     := 0x07FFFF    =: 524287.000000
c_min     := 0x070000    =: 458752.000000
   The above gave a final b=312756; b/c_min=0.681754. Ok.
   delta_f  = 4928 Hz (theoretic "positive" peak deviation), 
   delta_f2 = 5626 Hz (theoretic "negative" peak deviation).
   But does the firmware really need to try 0x7, 0x3, 0x1 if 0xF in the LSBits of 'c'
   didn't work ? How about the following .. :
c_center  := 0x017FFF
c_max     := 0x01FFFF
c_min     := 0x010000
   The above gave a final b=15464; b/c_min=0.235962. Ok... BUT :
   delta_f  = 4984 Hz (theoretic "positive" peak deviation), 
   delta_f2 = 9955 Hz (theoretic "negative" peak deviation).
   ->  severly distorted modulation in this case !
c_center  := 0x0A7FFF    =: 688127.000000
c_max     := 0x0AFFFF    =: 720895.000000
c_min     := 0x0A0000    =: 655360.000000
   c=0x0A.... above gave a final b=605408; b/c_min=0.923779. Ok (BEST solution)
   delta_f  = 4901 Hz (theoretic "positive" peak deviation), 
   delta_f2 = 5386 Hz (theoretic "negative" peak deviation).
   ->  least distortion, but still far from being 'HiFi' .

a := int(f_vco / f_out)  =: 84.000000
  Oops.. with f_out=145 MHz, a = 6, that's too small for a FRACTIONAL output divider (a>=8) !
b := 1000; for simplicity, start with an almost arbitrary value:
f_out_center := f_vco / ( ( a + b / c_center ) )  =: 10714100.357784
f_out_max    := f_vco / ( ( a + b / c_max )    )  =: 10714108.782952
delta_f := f_out_max - f_out_center  =: 8.425168
b := int(b * (deviation / delta_f))  =: 593459.000000
  Try one more iteration. b_out shouldn't change much now:
f_out_center := f_vco / ( ( a + b / c_center ) )  =: 10605400.251972
f_out_max    := f_vco / ( ( a + b / c_max )    )  =: 10610301.563703
f_out_min    := f_vco / ( ( a + b / c_min )    )  =: 10600014.208257
delta_f  := f_out_max - f_out_center  =: 4901.311731
delta_f2 := f_out_center - f_out_min  =: 5386.043715
b := int(b * (deviation / delta_f))  =: 605408.000000
  b/c_min must be less than 1.0 : 
b/c_min   =: 0.923779

- - end of the FM example for 10.7 MHz TX-IF with 4000 Hz deviation - -




  For large FM deviation, the upper 4 bits SET in the 20-bit denominator (c)
  may cause the numerator (b) exeed the numerator in si5351.c : Si5351_GetOutputDividerParamsForFM().
  Example:
f_vco     := 900MHz      
f_out     := 93.2MHz  // let's play 'FM broadcaster'
deviation := 75kHz    // wide FM .. 50 or 75 kHz *deviation* (bandwidth 200 kHz)
c_center  := 0x0F7FFF     =: 1015807.000000
c_max     := 0x0FFFFF     =: 1048575.000000
c_min     := 0x0F0000     =: 983040.000000
a := int(f_vco / f_out)   =: 9.000000
          // a=9 is just high enough for the FRACTIONAL output divider (a>=8).
b := 1000 // again, start iterating with an arbitrary value
f_out_center := f_vco / ( a + b / c_center )   =: 99989062.985501
f_out_max    := f_vco / ( a + b / c_max )      =: 99989404.731317
delta_f  := f_out_max - f_out_center  =: 341.745816
b := int(b * (deviation / delta_f))  =: 219461.000000
  Try one more iteration. b_out shouldn't change much now:
f_out_center := f_vco / ( a + b / c_center )   =: 97655762.976990
f_out_max    := f_vco / ( a + b / c_max )      =: 97727355.571858
f_out_min    := f_vco / ( a + b / c_min )      =: 97579515.466336
delta_f  := f_out_max - f_out_center  =: 71592.594867
delta_f2 := f_out_center - f_out_min  =: 76247.510654
b := int(b * (deviation / delta_f))  =: 229906.000000
f_out_center := f_vco / ( a + b / c_center )   =: 97546928.571177
  Again, the final b/c_min must be less than 1.0 : 
b/c_min   =: 0.233872

  Revise f_vco (in the firmware, using the fractional PLL FEEDBACK) :
f_vco := f_vco * (f_out/f_out_center)  =: 859893809.355517
  Double-check f_out_center; it should equal f_out now :
f_out_center := f_vco / ( a + b / c_center )  =: 93200000.000000

- - end of the WFM example for 93.2 MHz with 75 kHz deviation - -


A test to compare the output phase noise when injecting the modulation..
  (A) into the lower 16 bits of parameter 'P2' of the PLL FEEDBACK DIVIDER
and
  (B) into the lower 16 bits of parameter 'p3' of a FRACTIONAL OUTPUT DIVIDER
      gave no significant 'measurable' difference - see details in
      dsPIC33EP_Si5351_Synth/Documentation/Si5351_FM_Tests_2021_11.txt .
      (we're going to use lower case p1,p2,p3 for the output divider,
                      and UPPER CASE P1,P2,P3 for the PLL FEEDBACK from here).

Pros and cons of both 'modulation methods' : 

(A) PRO: Can be used to frequency-modulate carriers of up to 200 MHz;
         no problem above 112.5 MHz, and not even a problem above 150 MHz.
    BUT: As shown further above, the REAL (measured) FM deviation
         depends on the 'sampling rate' (how many thousand times the
         Si5351 gets reprogrammed per seconds), and also on the
         values currently in the 'modulator', P3. Especially at
         very low deviations, this may cause audio distortions,
         thus the decision was made to implement BOTH methods
         in the synthesizer firmware (si5351.c); at least for a start.
    CON: With f_vco = f_ref * ( 512 + P1 + P2/P3 ) / 128 ,
          ( modulation injected HERE-------' )
         this method modulates the internal VCO frequency,
         so the modulated VCO cannot be used to feed other,
         non-modulated OUTPUT channels.
    PRO: When only used for SLOW SWEEPS, ultimately linear.

(B) PRO: With f_out = f_vco * 128 / ( 512 + p1 + p2/p3 ) ,
          ( modulation injected HERE ---------------' )
    CON: Non-linear, regardless of his the modulation is injected
         into the lower 16 bits of p2 or p3 (details in Si5351_FM_Tests_2021_11.txt).
    CON: Can only be used for output frequencies (1st harmonic) up to 112.5 MHz, because
     > FRACTIONAL divider values are between 8  +  1 / 1,048,575 and 2048. 
     > This means that if any output is greater than 112.5 MHz (900 MHz/8), 
     > then this output frequency sets one of the VCO frequencies.
    (besides that, above 150 MHz, the only available OUTPUT divider ratio is FOUR.)

    