Emulated DDS principles

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This is an attempt at an explanation of the emulated DDS process in  simple terms. The assumption is made that you are familiar with the basics of programming such as binary arithmetic and look-up tables. Commercial chips are available which are very high speed devices specially designed for DDS. The simple DDS generator in this project is a standard low-end microprocessor which emulates the DDS function with software. 

At the core of the process the DDS software executes a tight loop:

The two 24 bit numbers are referred to as the Phase Accumulator and the Phase Increment. The phase increment is constant while the DDS is generating a particular output frequency. The phase accumulator starts at zero and continues to grow in value (in phase increment steps) until such time that the 224 limit overflows and the process starts over.

The first important parameter is the frequency at which the loop above operates, we will refer to this as the Sampling Frequency. This is obviously a function of the microprocessor clock frequency and the number of clock cycles required to execute 1 iteration of the loop. For the design in this article the microprocessor clock (crystal) frequency is a nominal 11.059 MHz but actually measures at 11.061 MHz and it requires 9 clock cycles to perform the loop. Thus the sampling frequency is 11061000 / 9 or 1229000 Hz.

Consider the case where the phase increment is 1. It will take 224 iterations of the loop before overflow takes place. In other words, if you were to measure the frequency of the overflow bit you would find it would be (sampling frequency) / 224 = 1229000 / 16777216  = 0.0732541 Hz. This frequency is referred to as the Phase Resolution of the loop and is the lowest frequency which can be generated by the loop. Furthermore, every frequency which can be generated by the loop is an integer multiple of this frequency. Setting the phase increment value to N  will generate a frequency of N x Phase resolution. Conversely, to generate a particular frequency F we simply set the phase increment value to F / phase resolution. As an example, for a frequency of 1000 Hz the phase increment would be set to 1000/ 0.0732541 = 13651. The important principle is that the loop iterates at a fixed frequency (sampling frequency) while the frequency of overflow is variable and is determined by the phase increment value. The frequency of overflow is the output frequency of our generator.

A full cycle of the phase accumulator from zero through to overflow represents 1 full cycle of the output waveform from zero to 360 degrees. So we can view the number in the phase accumulator at any instant as representing the phase of the output cycle in steps of 360/224 degrees. We could also have a pre-calculated lookup table telling us what the voltage of the waveform would be at that phase instant on a scale of 0 to 255 (8 bits). Send this voltage value to an output port with a digital to analogue converter attached and bingo - we have our output waveform.

There is a bit of snag - our lookup table would require 224 entries, a bit much for our micro ! Luckily we don't have to use all 24 bits of the phase accumulator. We can ignore less significant bits with a trade off in resolution. If we only consider the most significant 8 bits of the phase accumulator, they can represent 256 values, each of these values represent the phase of the output waveform in steps of 360/256 degrees. This is good enough for our application and the 256 byte lookup table per waveform is within the capabilities of our micro.

In this implementation an AT90S2313 is used as the DDS generator micro. At switch-on the micro initialises to generate 1000.0 Hz sine wave. The frequency can be changed by the user using a number of buttons. A PIC micro monitors these buttons. When a frequency change is made by the user, the PIC calculates the phase increment required to generate the new frequency and sends this to the DDS micro via the serial interface.