I was lucky to get one of the DXR700-710 variants of the commonly available 6 GHz units that some of us have been modifying to get on 5.7GHz. The 6 GHz unit is known as a DXR700-768.

THE TX UNIT (YIG IS UNDER THE ORANGE PCB CIRCLE)		THE RX UNIT

This unit is in the same solid housing as the 768 but differs in that it uses YIG (Yttrium Iron Garnet) oscillator modules instead of the interdigital negative resistance oscillator found in the 768.

There are 2 YIGs, one for TX and one for RX.

The PLL chip is an Analogue devices unit (ADF4118) that has an internal 3GHz prescaler and uses 2, 21 bit load for chip setup and division ratios. It is, in fact the same word style as the LMX2326 chip in the 768 unit.

The YIGs run at their fundamental frequency and are prescaled by four, by an Agilent Prescaler chip that runs up to 12GHz. This divided down frequency is than passed to the ADF4118 PLL chip prescaler input.

We have had experiences in the past with the 5GHz unit where we had the following issues:-

• VTCXOs need to be locked together or disable one and run off one only – done for transcieve reasons..

• Phase noise spurs and loop instability.

• Beats and RF leakage between two PLLs running together.

We addressed the issues as follows..

VTCXOs and the ability to transcieve properly.

Disable the RX VTCXO and back feed the buffered TX reference oscillator to the RX PLL reference input. It’s fairly easy to do by removing the single element 74HC04 buffer and cap couple through.

Disable the power supply to the ref osc in the RX as well.

Phase noise issues.

It has been found that using too higher division ratios causes the phase noise to be bad. We have played around with different references both in the 5GHz and now the 10GHz unit. We have settled on 2MHz steps that results in a division ratio of 20 to give a 500kHz reference at the PLL, multiplied by four effectively, (due to the divide by four Agilent prescaler) gives us a 2 MHz step at 10GHz.

Beating PLLs

To fix this, we need to change the frequency so the two PLLs are not running on exactly the same frequency.

To do this, we use a 2MHz offset.

While the unit is in RX, the TX PLL will be the wanted LO frequency + 2MHz.

When in TX, the RX PLL will move up 2MHZ, so wanted LO + 2MHz.

EG We want a 10224MHz LO for a 144MHz IF.

So In RX

TXPLL=LO+2MHz

And in TX

RXPLL=LO+2MHz

In a steady state,

Mode	TXPLL	RXPLL
RX	10226	10224
TX	10224	10226

Keith ZL1BQE and I (ZL1SWW) developed a board to control both PLLs from one micro, a Motorola 68HC908qy4. The chip is an SMD unit that offers all the port pins we need.

A few nights talking on a simplex and passing bits of assembler routines between each other, we came up with a working unit. I had already designed a PCB for the unit and used ISP (In system programming) the chip that has a small boot loader to allow me to reprogram the micro in circuit.

Believe me, several programming attempts were needed before we got it running the way we wanted!!

The micro controls:-

• Both PLL chips.

• The 2MHz “anti beat” offset

• TX sequencer.

The system we have is frequency agile by serial control, so the LO frequency can be placed wherever it suits. (I have found that it will lock to 9935 MHz for a 433MHz IF but sensitivity is down, most likely due to IF filtering).

In a contest situation, you may need to shift the IF in the field without a PC so there is provision to move by pulling down a pin on the micro to change to a different preset. The presets are held in the micro’s flash.

To get the system running, there is very little you have to do from the RF perspective. Most changes lie in the digital domain!!

Circuit Operation / Explanation

The PLLs are controlled by SPI data lines CLK, Data and Enable.

All the lines are paralleled up with the exception of the Enable line. Data is sent twice during a power up or a TX / RX transition..

On Power up the TX data is sent to the TXPLL and then the RX data is sent to the RX PLL. If you have connected Lock Detect LEDs to each chip, you will see the delay as the PLLs load.

The SPI data is clocked through synchronously 24bits at a time but only 21 bits are used by the PLL for the load. The first part sets up the Charge pump and LD LED function, the other load sets up the reference division ratio. Once all data is loaded to the PLL chip, enable is toggled to transfer what is in the PLL shift register, into the relevant areas in the PLL chip. All this happens for each PLL chip in turn.

Four port pins on the micro are needed to control two PLLs.
DATA
CLOCK
TX ENABLE
RX ENABLE

The units run off a 10 volt supply so two voltage regulators are used, to supply the PLLs and the other to supply TX & RX sections respectively.

The regulators run all the time and the TX / RX supplies are switched with a small 5v relay inside the module’s cavity.

The control board comprises of the following functions.

• PLL control / Sequencing Micro.

• VTCXO frequency fine adjust POT.

• Two LM317 voltage regulators for 10v supplies.

• Optional TX RF output control pot.

The board resides on the TX side of the casing as there is more room and the DB25 socket to connect to the outside world is on that section anyway.

Construction.

Using the PCB is the easy way to go as it makes it easier especially with the SMD micro.

Steps I take to build and test progressively.

1. Etch the board and drill where needed. Put all links on the fibreglass side of the board. All components sit on the copper side of the board with the exception of some of the passive ones that you may elect to put underneath.

2. Mount the voltage regulators so that the packages nearly butt up against the side of the board by about 2mm. Make both regs sit in line for tidiness.

3. Put in the 12 pin header socket – from the fibreglass side of the board.

4. Place board in the unit the right way around to be able to mark out and cut a piece of aluminium to fit snugly in the casing for heat sinking the regs. Should be able to use M3 holes in casting to mount the heat sink. Once done, mount regs to heat sink with insulating hardware. Drill holes in PCB to connect to heat sink for mechanical rigidity. Check lack of continuity between reg tag and heat sink, they should be isolated.
   
   

5. Install reg components and test for correct voltages.

6. From there, install other components.
   

7. You should be able to test the sequencer part of the micro by installing LEDs via current limiting resistors to the open collector outputs of the transistors. Make sure PTB0 (pin ??15) is held low for sequencer to work.
   

8. Pull down the PTT pin on the micro and see if the LEDS light in succession. Releasing the PTT line will make them go out the reverse of way they came on.

9. Assuming you have the PLL LD LED connected, you should be able to install the board in the bottom half of the casing and test the TX PLL.
   

10. Put supply voltage on and see if the PLL LD LED comes on for a second and then goes out. If it does this, then there is a big chance that the PLL is loading and locking OK. We have hard coded the PLL to wake up on 10224 MHz.

11. Isolate the VTCXO inside the RX unit. Please see the photo of what to do.
    
    

12. Cut up a piece of Vero for the RX connection and attach some header pins (12) to the board, and connect up as per the accompanying schematic.
    
    

13. You should be bringing out the +10v continuous for the PLL, 10v switched for the RX section, the 3 SPI data lines, TCXO reference and the LD LED.
    

14. The LD LED supply HAS to run from the 5v supply via a 1k resistor. Possible damage to the PLL chip could occur otherwise, also the LED will not go fully out when locked either.
    

15. The Image reject mixer pin needs to be pulled up to 10v via a 10K resistor.

16. Connect all relevant signals up to the DB25 female socket in a tidy manner. Please see my standard pinout for connecting.

I have built a 10 GHz filter that will be explained later as I get time..

The Unit is housed in a watertight case that I luckily procured from a friend. It's an ex cable TV distribution amp..

This is the DXR in a box. The little board at the bottom is the  IF switching / input attenuator. Also has RF sensing circuitry for PTT control. This feeds the micro PTT pin. SSB hang time controlled by this little board as well. The right side shows the filter and PA section with the output relay. This pic shows a flexible cable for 10Gig RX - ths won't be staying long!! Lossy and unnecessarily long!! TX output is nominally 4Watts. Note BNC located for IF in within bottom left cable entry point. Programming port does the same at the other end behind the PA. Has nice waterproof cap to cover up the 3.5mm stereo socket. Uses LM1084 LDO for 10.5V supply for the PA. Its alot cheaper than the LT1084 equivalent.

The LNB feeder I am using is an old LNB from a SKY dish that had the plastic cover broken off. This Idea came from Tim ZL2RST. The probe feed is quite a way from the back of the waveguide as the LNB is for 12GHz and it is tapered so the back part will not support 10 GHz wave propagation. There  is a probe which we work against.  I have yet to check return loss  but will when I get time. Seems to work ok though!!

A few Piccies.... Top Left - Modded SKY LNB, have bulkhead N connector mounted to teh inside chassis of the LNB - takes pressure off the poor little SMA at the front!! Top Right - Is Harry ZL1BK finding the microwaves making his head warm? Is that why he is ducking? - No he just happened to pick something up as I was taking the pic. Got ro tidy up those huge lengths of feedline but ran out of time for test day.  Dish is a 40cm IHUG dish. And no, it's not transmitting!! Right - Yeah that's me, ZL1SWW using my new creation. Speaking to Steve ZL1TPH and later Brian ZL1AVZ.  Max distance that contact was 60km. Can do beetr next time i am sure! Tripod recently procured form the Cambridge junk sale.  Good price too!

Protel PCB patterns and preprogramed devices most likely available on request, just email me.