<excerpt>Dear Fellow Colleagues:


In a recent question, John Lin asked about the problems of covering all
the combinations in a SCSI backplane investigation.  Of course, the
number of combinations is very large but with care it is manageable.  Use
of symmetry and a matrix of loading cases is very helpful.  However,
there is an underlying resonance problem with all multi-drop busses seems
to be related to the value of the per slot reactive elements, especially
the stub reactance and the rise/fall time of the transceivers used on the
bus. 


Scott McMorrow's recommendation to use an .AC investigation of the
multi-drop structure (with terminations) is an excellent suggestion to
incorporate in your analysis.  If one computes the .AC driving point
impedance at a given point on the bus, you will see resonance peaks which
appear to be a parallel type resonance, i.e., high impedance at the
driving point. This can be made into a graphical result with most SPICE
tools.


You will also find that the time domain analysis of the same bus will
show ringing at nearly the same frequencies you saw in the .AC analysis. 
This ringing is excited by rise/fall times of the drivers and its impact
is related to the speed of the drivers.  I am not sure that the driver
dynamic impedance makes much difference.  The most common situation is
that the active driver when proceeding to the high state goes from a low
value to near turned off and all others are tri-stated.  Under these
conditions, the bus looks like a lossy resonator and generally the
ringing continues after state changes from low to high. Depending on the
data rate, the ringing can have a duration over a substantial portion of
the cycle.   


As stated, the amount of ringing and its duration is related directly to
the rise time of the active driver and for that reason, controlled
risetime drivers are recommended.  Other effects like split backplanes,
cables in conjunction with backplanes, redundant driving, etc. only
complicates this problem. Bussed clocks are subject to the same problems
and for that reason, point to point serial terminated topologies (for
CMOS) are better.


Sincerely,


ed sayre & the NESA staff</excerpt>


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|       NORTH EAST SYSTEMS ASSOCIATES, INC.       |

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|     "High Performance Engineering & Design"     |

+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+

| Dr. Ed Sayre            e-mail: esayre@nesa.com |

| NESA, Inc.              http://www.nesa.com/    |

| 636 Great Road          Tel +1.978.897-8787     |

| Stow, MA 01775 USA      Fax +1.978.897-5359     |

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