Doug, Mark, Ken, and others,


Thanks for the discussions and comments on my paper <smaller>"Quantifying
Decoupling Capacitor Location"</smaller> presented in the 2000 EMC
symposium. I feel it may be useful to reiterate some conclusions drawn
from the work reported in the paper.


(1) It is commonly believed that an SMT decoupling capacitor has an
effective frequency range, which is determined by the total inductance
associated with the interconnects connecting the capacitor to the power
and ground planes. However, this is not the case for the decoupling
capacitors placed sufficiently close to the power or ground pin of an
active device. They tend to be effective up to several GHz ("An
experimental investigation of 4-layer printed circuit board decoupling",
Hubing et. al.). We denote this phenomenon local decoupling. 

(2) Local decoupling, we found, is due to the inductive coupling between
the closely spaced vias. Therefore, it is a function of the spacing
between the IC and the decoupling capacitor, as well as the power/ground
layer separation.

(3) For thin power/ground layers (10 mils or less), local decoupling is
negligible. All capacitors are global decoupling capacitors, and their
locations relative to ICs are unimportant.

(4) For thick power/ground layers, however, local decoupling may be
dominant. Placing decoupling capacitors in proximity to ICs may be
beneficial in mitigating power bus noise.

(5) It is worth noting again, that the noise mitigation benefits of a
local SMT decoupling capacitor extend over a wide frequency range, well
beyond the series resonance frequency limiting the effectiveness of a
globally placed decoupling capacitor.


Thanks,


Jun Fan


Ph.D.

Research Assistant

Electromagnetic Compatibility Laboratory

University of Missouri-Rolla

Rolla, MO 65409





At 03:57 PM 11/13/00 -0700, you wrote: 

>>>>

<excerpt><fontfamily><param>Arial</param><color><param>0000,0000,ffff</param><smaller>Mark
& Doug,

How do you interpret that?  

Ken

</smaller></color></fontfamily><smaller><fontfamily><param>Times New
Roman</param>-----Original Message-----

<bold>From:</bold> owner-si-list@silab.eng.sun.com
[mailto:owner-si-list@silab.eng.sun.com]<bold>On Behalf Of</bold> Mark
Gill

<bold>Sent:</bold> Monday, November 13, 2000 11:16 AM

<bold>To:</bold> 'Doug Brooks'; Thomas Jackson;
si-list@silab.eng.sun.com

<bold>Subject:</bold> RE: [SI-LIST] : deCoupling caps and there
placement


</fontfamily></smaller>

<smaller>Folks - Just a note on the UMR work.  To quote a UMR sponsored
paper for the 2000 EMC symposium, "Quantifying Decoupling Capacitor
Location", the paper states, 

</smaller>

<smaller>"A more recently published study of decoupling capacitors and
printed circuit boards as ensembles concluded that for printed circuit
boards with both power and ground planes, all decoupling capacitors are
shared in the frequency range in which they are effective; hence, the
location of the decoupling capacitor on the board is unimportant [4].
This study considered multi-layer boards with closely spaced layers and
its conclusions may have been extended beyond the region of validity of
the study."

</smaller>

<smaller>[4] T. Hubing, J. Drewniak, T. Van Doren, and D. Hockanson,
"Power Bus Decoupling on Multilayer Printed Circuit Boards," IEEE
Transactions on Electromagnetic Compatibility, Vol. 37, No. 2, pp.
155-166, May 1995.

</smaller>

<smaller>Regards,</smaller> 


<smaller>Mark Gill, P.E.</smaller> 

<smaller>EMC/Safety/NEBS Design & Compliance</smaller> 

<smaller>C-MAC Engineering Design Services</smaller> 



<smaller>-----Original Message-----</smaller> 

<smaller>From: Doug Brooks
[<<mailto:doug@eskimo.com>mailto:doug@eskimo.com]</smaller> 

<smaller>Sent: Monday, November 13, 2000 12:23 PM</smaller> 

<smaller>To: Thomas Jackson; si-list@silab.eng.sun.com</smaller> 

<smaller>Subject: RE: [SI-LIST] : deCoupling caps and there
placement</smaller> 



<smaller>But, I too would call your attention to an article that appeared
in PC 

Design Magazine in March, 1998 titled "An Interview With Todd Hubing" (a 

reprint is available in the "articles" section of our web site at 

<<http://www.ultracad.com>http://www.ultracad.com). Todd qualified the
comments in the article you 

referenced as applying only to boards where the power planes were 10 mils 

or less apart. For more conventional structures he commented that "closer 

is better".</smaller> 


<smaller>There has been a great deal of misinterpretation of what the
results meant 

in Todd's earlier article, and the Interview was an attempt to help
clarify 

some of the questions.</smaller> 


<smaller>Doug</smaller> 



<smaller>At 07:42 AM 11/13/00 -0800, you wrote:</smaller> 

<smaller>>I would like to call you attention to:</smaller> 

<smaller>></smaller> 

<smaller>>"Power Bus Decoupling on Multilayer Printed Circuit Boards" by
Hubing,</smaller> 

<smaller>>Drewniak, Van Doren and Hockanson, published in the May 1995
IEEE</smaller> 

<smaller>>Transactions on Electromagnetic Compatibility, Vol. 37,
No.2.</smaller> 

<smaller>></smaller> 

<smaller>>Among their conclusions is that "on printed circuit boards that
do have</smaller> 

<smaller>>internal power and ground planes, all decoupling capacitors are
shared in</smaller> 

<smaller>>the frequency range in which they are effective (typically
below 200-300</smaller> 

<smaller>>MHz), and the location of a decoupling capacitor on the board
is relatively</smaller> 

<smaller>>unimportant."</smaller> 

<smaller>></smaller> 

<smaller>>It appears to be more important to have the shortest possible
connections</smaller> 

<smaller>>between the decoupling capacitors and the power and ground
planes than where</smaller> 

<smaller>>they are on the board.</smaller> 

<smaller>></smaller> 

<smaller>>Thomas L. Jackson, P.E.</smaller> 

<smaller>>Staff Product Development Engineer</smaller> 

<smaller>>Network Access Development</smaller> 

<smaller>>Systems Solutions Group</smaller> 

<smaller>>FUJITSU MICROELECTRONICS, INC.</smaller> 

<smaller>>3545 North First Street</smaller> 

<smaller>>San Jose, CA  95134-1804</smaller> 

<smaller>>telephone: (408) 922-9574</smaller> 

<smaller>>facsimile: (408) 922-9618</smaller> 

<smaller>><<http://www.fujitsumicro.com>http://www.fujitsumicro.com</smaller> 

<smaller>></smaller> 

<smaller>></smaller> 

<smaller>></smaller> 

<smaller>>-----Original Message-----</smaller> 

<smaller>>From: jrbarnes@lexmark.com
[<<mailto:jrbarnes@lexmark.com>mailto:jrbarnes@lexmark.com]</smaller> 

<smaller>>Sent: Monday, November 13, 2000 6:41 AM</smaller> 

<smaller>>To: kowal@dnpg.com; si-list@silab.eng.sun.com</smaller> 

<smaller>>Subject: Re: [SI-LIST] : deCoupling caps and there
placement</smaller> 

<smaller>></smaller> 

<smaller>></smaller> 

<smaller>>Keith,</smaller> 

<smaller>>My approach is to put bypass capacitors as close as possible to
the power</smaller> 

<smaller>>pins</smaller> 

<smaller>>on a chip.  Whether we are using a multilayer card with ground
and power</smaller> 

<smaller>>planes,</smaller> 

<smaller>>or a double-sided card with ground gridding, we will almost
always have more</smaller> 

<smaller>>connections to and more copper for ground than for any one
supply voltage.</smaller> 

<smaller>>Thus</smaller> 

<smaller>>the path from a bypass capacitor to ground is usually shorter
and wider than</smaller> 

<smaller>>the</smaller> 

<smaller>>path to a supply voltage.  This results in:</smaller> 

<smaller>>*  Faster response by the capacitor, due to shorter transit
time in the</smaller> 

<smaller>>microstrip/stripline between the chip and the</smaller> 

<smaller>>    capacitor(s)--about 1/6 ns per inch for FR-4
boards.</smaller> 

<smaller>>*  More return-paths to the chip for the transient current,
which reduces</smaller> 

<smaller>>the</smaller> 

<smaller>>inductance, impedance, L * dI/dt drop, and</smaller> 

<smaller>>     maybe radiated emissions by the magnetic fields of the
various paths</smaller> 

<smaller>>partially cancelling one another.</smaller> 

<smaller>>*  Smaller loop area for the transient currents,
ditto.</smaller> 

<smaller>></smaller> 

<smaller>>Since transient currents are my major concern, I try to put the
highest</smaller> 

<smaller>>frequency-response capacitors (typically 220pF NPO ceramics for
clock and</smaller> 

<smaller>>phase-locked loops (PLL's)) right next to their corresponding
power pins.</smaller> 

<smaller>>Then</smaller> 

<smaller>>I put lower frequency-response capacitors (typically a 100nF
X7R ceramic for</smaller> 

<smaller>>each power pin or cluster of power pins) as close as possible
to their</smaller> 

<smaller>>corresponding power pins.  Next I consider how to route
traces/vias to bring</smaller> 

<smaller>>power and ground to the power-pin/ground-pin/bypass capacitor
cluster.  If I</smaller> 

<smaller>>can</smaller> 

<smaller>>I will bring in power and ground right next to each other, but
I don't worry</smaller> 

<smaller>>too</smaller> 

<smaller>>much if the power and ground connections are on opposite sides
of a cluster.</smaller> 

<smaller>></smaller> 

<smaller>>Depending on the complexity and package size of the chip, I
will also put 1</smaller> 

<smaller>>to 4</smaller> 

<smaller>>bulk ceramic capacitors (typically 2.2uF Y5V ceramics) on each
supply</smaller> 

<smaller>>voltage</smaller> 

<smaller>>within 1 inch of its power pins,  trying to "surround" the
chip.  If I have</smaller> 

<smaller>>a</smaller> 

<smaller>>bunch of small chips in a small area, I may use just one bulk
ceramic</smaller> 

<smaller>>capacitor</smaller> 

<smaller>>for the entire clump.</smaller> 

<smaller>></smaller> 

<smaller>>Finally I put bulk aluminum electrolytic or tantalum capacitors
(10uF and</smaller> 

<smaller>>up):</smaller> 

<smaller>>*  Near the power connector(s) to a card.</smaller> 

<smaller>>*  Near power connectors to other cards/devices.</smaller> 

<smaller>>*  Near the corners of the supply-voltage domain.</smaller> 

<smaller>>*  Near "power hog" components, trying to have one within 2
inches of every</smaller> 

<smaller>>power pin on that supply voltage ("coffee</smaller> 

<smaller>>    cup" rule).</smaller> 

<smaller>></smaller> 

<smaller>>                                                    John Barnes
 Advisory</smaller> 

<smaller>>Engineer</smaller> 

<smaller>>                                                    Lexmark
International</smaller> 


<smaller>.</smaller> 

<smaller>************************************************************</smaller> 

<smaller>Doug Brooks' book "Electrical Engineering for the
Non-Degreed</smaller> 

<smaller>Engineer" is now available. See our web site for
details.</smaller> 

<smaller>.</smaller> 

<smaller>Doug Brooks, President              doug@eskimo.com</smaller> 

<smaller>UltraCAD Design, Inc.          
<<http://www.ultracad.com>http://www.ultracad.com</smaller> 



<smaller>**** To unsubscribe from si-list or si-list-digest: send e-mail
to</smaller> 

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UNSUBSCRIBE</smaller> 

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