From: Lawrence Butcher ([email protected])
Date: Sat Feb 24 2001 - 17:59:01 PST
I have an idea. I wonder if the people in this list with RF experience
(or a 3D field solver) might be willing to comment on whether it is
possible, or just blowing smoke. (I hope it is at least entertaining.)
I have read the R-S-P paper below. Like others, I was curious why the
Cap VIA Escape technique used only one via per cap contact.
In boards I have built, I have tried to use 2 vias per cap contact. The
intuition is that by paralleling the contacts, the contribution to the
ESR due to board-layout would be halved. I've been thinking about this,
and that idea might not be true. Who knows? I have new idea below.
If you hook a cap to a board with 2 parallel widely spaced 10 cM wires,
you will have a bad L term in the circuit.
If you twist the wires, or hook the capacitor to the board with Coax,
the situation would be different. There is no loop area, no net magnetic
field, so there should be no contribution to the L due to wire length.
We are all aware that mounted Axial lead caps have a bigger inductance
than mounted Radial lead caps. In general, the longer the distance
between the contacts on a capacitor, the higher the mounted inductance.
We usually expect to see an L term in a ceramic capacitor which is
related to the cap length. If the idea about the cap at the end of
a twisted pair is true, can this be extended to the PC board?
Here is an idea for a different layout of vias.
()++++++++++++++| | |
------------|++| | | Cap body
------------ -------- | |
| |+++() | | (top --------\/-------- (side
| |---- | | view) --------/\-------- view)
| |---- | | ** **
| |+++() | | ** **
------------ -------| ----------- ** ----- GND plane
()++++++++++++++| -------------------- PWR plane
That \/ area represents the place on the PCB surface where the via
escape conductors run parallel, and where current is flowing in the
opposite direction as it is in the capacitor. (To make things simple,
I didn't include the possibility of running traces on another layer
actually under the cap contacts.)
My speculation here is that the magnetic field due to the loop below
the top of the PCB will be opposite to the magnetic field due to the
loop which passes through the Cap. These magnetic fields will subtract,
resulting in a smaller magnetic field than the best possible normal
mounting. I am imagining that by crossing the wires, the layout is
actually adding a negative L term below the surface to the positive
L term above.
If true, and if the R added by the extra wires isn't too large, it
might be possible to mount a capacitor and have it resonate at a
frequency which is HIGHER than it's self-resonance frequency.
So that's the idea. Symmetric layout designed to create magnetic fields
which offset the fields below the bypass cap, resulting in less energy
stored in the magnetic field, less corresponding L, giving lower ESR
at high frequencies.
What do you think? Let the generous and/or sarcastic comments begin.
(You should be able to make similar arguments that you can improve the
mounted L of an axial-lead capacitor by adding more contacts, so the
layout is symmetrical with no large unbalanced loops for fields to store
energy in. For instance, you could put the + terminal in the middle of
the cap and surround it with 3 or 4 closely spaced - terminals. Have to
get the cap vendors to make caps with 4 or 5 wires, though.)
> X-Unix-From: [email protected] Thu Feb 22 05:16:14 2001
> From: "Kai Keskinen" <[email protected]>
> To: "'[email protected]'" <[email protected]>
> Subject: RE: [SI-LIST] : CHIP INDUCTOR Q AND L AS FUNCTION OF ORIENTATION?
> Date: Thu, 22 Feb 2001 08:01:58 -0500
> MIME-Version: 1.0
> X-Orig: <[email protected]>
> See the paper by Tanmoy Roy, Larry Smith, and John Prymak called ESR and ESL
> of Ceramic Capacitor Applied to Decoupling Applications.
> Kai Keskinen
> Equipment and Network Interconnect
> Nortel Subsystems and Performance Networks (NSPaN)
> (613)-765-3506 (ESN 395)
> [email protected]
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