From: Zhiping Yang ([email protected])
Date: Thu Feb 22 2001 - 17:32:38 PST
Hi,
If interested, please forward you resume to [email protected].
Thanks.
Have a good day,
Zhiping
ASIC Signal Integrity Engineering:
------------------------------------------------------------------------
DESCRIPTION:
Join Cisco Systems, ISBU ASIC Signal Integrity Group for an
exciting opportunity to share the responsibilities for the design,
analysis and testing of high-speed interconnects. You will
interface with ASIC and System Design teams as well as
technology providers to solve complex design challenges.
BACKGROUND:
You will contribute to the signaling and interconnect
technology selection, definition and simulation of high-speed
interconnects using simulation tools such as XTK and
HSPICE. The validation of all of the above using TDR,
Network Analyzer, Oscilloscopes and other lab equipment's.
You will also play a key-role in the ASIC I/O Buffer
structure definition and selection. A solid understanding
of transmission line fundamentals and demonstrated practical
expertise in signal integrity is required.
You will assess timing, noise margin, crosstalk, signal loss
and signal integrity of all clocks and critical data signaling
and develop noise and timing budgets. Familiarity with high
speed I/Os such as HSTL,SSTL, LVDS, LVPECL, CML and
memory technologies as QDR, DDR is required.
Understanding the challenges required to solve source
synchronous bus design is essential.
Experience in High Speed ASIC design is a plus. Good
documentation skills, communication/customer interaction
skills also required.
LOCATION:
San Jose, CA
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This archive was generated by hypermail 2b29 : Tue May 08 2001 - 14:30:55 PDT