RE: [SI-LIST] : CHIP INDUCTOR Q AND L AS FUNCTION OF ORIENTATION?

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From: Ray Anderson (Raymond.Anderson@eng.sun.com)
Date: Thu Feb 22 2001 - 16:00:43 PST


Sandor-

I don't think you are going out on a limb at all. I got the impression
that most of the other commentors were answering a different question
than was asked.

Both chip capacitors and inductors can have varying parasitics releated
to their mouinting orientation. However the causes and effects are
usually different for caps and inductors.

The paper by Roy, Smith and Prymak addresses issues with capacitors.
Inductors were not investigated or considered.

Those who pointed out the difference in mounted inductance in caps
due to mounting pad geometries and via arrangements were correct in
their assertions, however I don't think those assertions are germaine
to the discussion of chip inductors and the effects of mounting orientation.

-Ray Anderson
Sun Microsystems.

>From: Sandor Daranyi <Daranyi@ali.com.au>
>To: si-list@silab.eng.sun.com
>Subject: RE: [SI-LIST] : CHIP INDUCTOR Q AND L AS FUNCTION OF ORIENTATION?
>Date: Fri, 23 Feb 2001 09:45:03 +1100
>MIME-Version: 1.0
>
>Hello All,
>
>I might be going out on a limb here, but I read Steve's original question
>differently. "Which way up the chip inductor is mounted" sounds like an
>assembly, not a layout related question, i.e. how Q and L is affected if the
>chip inductor is placed up-side-down.
>
>If this is the case, I'd guess Q can vary in some cases. For example chip
>components with planar spiral inductors usually have an asymmetric vertical
>structure (as in http://www.avxcorp.com/docs/techinfo/aculmlc.pdf Fig 1)
>which seems to have a "right way up". The mentioned example is in an 1206
>or 0805 package, so it's not hard to mount it up-side-down which means that
>the small inductor structure will be closer to the board with possibly more
>parasitic capacitance to any copper structure under it. In theory, at
>least. This should influence Q somewhat.
>
>Steve, what's the article you've mentioned?
>
>Regards,
>
>Sandor
>
>------------------------------------------------------------------
>Sandor Daranyi
>Aristocrat Technologies Australia Pty Limited
>Electronic Engineering Department
>daranyi@ali.com.au
>
>-----Original Message-----
>From: Ken Cantrell [mailto:Ken.Cantrell@srccomp.com]
>Sent: Friday, 23 February 2001 3:28
>To: Cruz, Jose; 'Kai Keskinen'; si-list@silab.eng.sun.com
>Subject: RE: [SI-LIST] : CHIP INDUCTOR Q AND L AS FUNCTION OF ORIENTATION?
>
>
>All,
>I ran across a paper by Harada, Sasaki, and Kami in the IEICE transactions
>that concluded that the number of vias per pad had a significantly greater
>effect on reducing inductance than the pad size/orientation. That is,
>given good pad construction as detailed in the Roy, Smith, and Prymak,
>increasing the pad size, or width to length ratio has less effect on
>reducing the mounted inductance than adding more vias. Harad, Sasaki, and
>Kami had typical reduction values of 500pF for configurations studied.
>IEICE Trans. Commun., Vol E83-B, No. 3, March 2000: "Controlling
>Power-Distribution Plane Resonance in Multilayer Printed Circuit Boards",
>Takashi Harada, Hideki Sasaki, and Yoshio Kami.
>
>Roy, Smith and Prymak do not discuss ringing effects of low ESR caps. Does
>anyone have any data/papers on that?
>Ken
>-----Original Message-----
>From: owner-si-list@silab.eng.sun.com
>[mailto:owner-si-list@silab.eng.sun.com]On Behalf Of Cruz, Jose
>Sent: Thursday, February 22, 2001 8:11 AM
>To: 'Kai Keskinen'; 'si-list@silab.eng.sun.com'
>Subject: RE: [SI-LIST] : CHIP INDUCTOR Q AND L AS FUNCTION OF ORIENTATION?
>
>
>
>-----Original Message-----
>From: Kai Keskinen [mailto:keskinen@nortelnetworks.com]
>Sent: Thursday, February 22, 2001 8:02 AM
>To: 'si-list@silab.eng.sun.com'
>Subject: RE: [SI-LIST] : CHIP INDUCTOR Q AND L AS FUNCTION OF ORIENTATION?
>
>
>See the paper by Tanmoy Roy, Larry Smith, and John Prymak called ESR and ESL
>of Ceramic Capacitor Applied to Decoupling Applications.
>Kai Keskinen
>Equipment and Network Interconnect
>Nortel Subsystems and Performance Networks (NSPaN)
>(613)-765-3506 (ESN 395)
>keskinen@nortelnetworks.com
>
>
>-----Original Message-----
>From: Steve Rogers [SMTP:SRogers@micromill.com]
>Sent: Thursday, February 22, 2001 6:27 AM
>To: 'si-list@silab.eng.sun.com'
>Subject: [SI-LIST] : CHIP INDUCTOR Q AND L AS FUNCTION OF
>ORIENTATION?
>I have recently read an article which suggests that the Q and Inductance of
>many chip inductors will differ depending upon
>which way up the inductor is mounted. Would anyone care to comment on this?
>Thanks in advance
>SGR
>
>
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