Re: [SI-LIST] : PCI length calculations

About this list Date view Thread view Subject view Author view

From: Scott McMorrow (scott@vasthorizons.com)
Date: Wed Feb 21 2001 - 23:07:50 PST


Suchitha,

Generally, problems occur with PCI busses which are designed
to the 5V signalling standard, but use 3.3V drivers. When this condition
occurs, there are no clamp diodes available for low to high transition
overshoot.

What you should look for is excessive ringing after rising edge
transitions. It is very likely that you will find ringback that
violates the threshold region. In order to find this, you will need to
use a high bandwidth oscillocope. First, start by probing all the
clocks at each pin of every device (not at the connector) and measure
the worst case clock skew. It should be less than 1ns to avoid
hold timing issues at the fast corners.

After you are sure that there is no significant clock skew, then use one
of the clocks as a baseline and measure setup and hold of
signals on the PCI bus (at the device pins) relative to that clock.
Here it helps to place the scope in infinite persistance mode.
The first place to look for issues will be on the upper 32 bits of the
bus, since these have the longest routing on the cards and
generally on the motherboard. At this point you need to begin
doing some detective work, since all PCI bus signals have identical
electrical and timing characteristics. (Except for Reset and a few
open collector lines.)

If the problem you have is a PCI bus problem, then you will eventually
see the problem on the scope. Look for any signals that are within
a window between 800mV and 2.0V during the setup and hold
region around the clock rising edge. Then, if you see something
close to this region, hit each of the parts with Freeze Spray and
see if the problem becomes worse. At low temperature the parts
will speed up, the edge rate becomes faster and the drive strength
goes up, making the problem worse. If you start off at room temperature,
with freeze spray you may find the part that is causing the problem.
This is usually a driver. The result of the driver's overdrive and
excessive edge rate will be felt at the receiver as ringback which
passes into the threshold region, causing false transitions.

There are other device level issues which can also cause problems,
such as package crosstalk and ill behaved ground clamp diodes.
On the newer designs with the new Hub architecture, problems can
arise from improper routing of the hub interface lines. This is a
high speed source synchronus bus which is extremely noise and
crosstalk sensitive. High bandwidth PCI masters can stress the
Hublink to the point that it fails, if not routed correctly.

We have seen many different PCI problems over the years.

regards,

scott

--
Scott McMorrow
Principal Engineer
SiQual, Signal Quality Engineering
18735 SW Boones Ferry Road
Tualatin, OR  97062-3090
(503) 885-1231
http://www.siqual.com

Suchitha.V@smartm.com wrote:

> Hello Scott, > > Thankyou for your eply. > > Could you please desribe the possible resonance conditions that > occur on a PCI bus? > You mentioned that short PCI busses that do not work over all > posssible conditions also exist. > Could you please mention some of these conditions? > > For example, my mother board has two 64-bit PCI slots connected to > Intel's 21154. > I find the following problems. > > 1) When gigabit ethernet cards (from Netgear) are inserted in these > slots, FTP operations at temperatures below 8 degree centigrade > causes the system to lock up. The system runs on Windows NT > server, service pack 6.0. > 2) Sometimes the system locks up after loading drivers for the > Netgear gigabit ethernet cards. > > I would like to know where to probe. > > Looking forward to your reply. > > Regards > suchitha > >

**** To unsubscribe from si-list or si-list-digest: send e-mail to majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu ****


About this list Date view Thread view Subject view Author view

This archive was generated by hypermail 2b29 : Tue May 08 2001 - 14:30:55 PDT