**From:** *Suchitha.V@smartm.com*

**Date:** Wed Feb 21 2001 - 13:29:18 PST

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Hello,

Thankyou for your reply.

Length(maximum) has not been specified in the PCI spec or elsewhere.

Practically, boards are routed with lengths of around 10-13 inches for

33MHz.

In my case, I have 8 loads, with a trace impedance of 60 ohms. Using a daisy

chain topology, with simulations,

for both corners, to meet the setup and hold times will determine my maximum

trace length. Am i correct?

In a case where there are 10 loads, to meet the setup and hold times, the

length will have to be lesser than with 8 loads.

Am i correct

I have the following questions:

Is there any other preferred topology for routing PCI bus signals? This is

other than Daisy chain topology.

In what way is REQ# and GNT# different from AD signals in regard to the

timing?

Can you explain?

Regards

suchitha

---------------------- Forwarded by Suchitha V/Apex Data Inc/01 on

02/21/2001 12:31 PM ---------------------------

From: Ingraham@andrew.ingraham on 02/21/2001 12:13 AM

To: Suchitha V/Apex Data Inc/01@Apex Data Inc

cc: si-list@si-list@silab.Eng.Sun.COM@SMTP@EXCHANGE

Subject: RE: [SI-LIST] : PCI length calculations

The PCI bus has no length specification.

*> How do you arrive at the maximum length for a PCI 33 MHz bus?
*

Best done by simulations using your intended configuration (numbers of

loads, routing topology, trace impedance), and best-case and worst-case

device models.

The signal from any device on the bus must propagate to all other devices

and remain at a valid level within 10 ns (at 33 MHz for bussed signals, much

less for REQ# and GNT#), compared to the driver driving the test load.

Usually this means waiting for at least one reflection to return from the

end(s) of the bus. More detail can be found in the PCI electrical spec.

*> I have done some calculations to arrive at the routed length required.
*

The presence of stubs and connectors tends to make simple calculations not

very useful.

*> But the length is much lesser than the PCI length specified for 33MHz(
*

*> which
*

*> assumes say 12 inches as maximum)
*

Where did this come from?

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