[SI-LIST] : Evaluating packages: A simple task or is it?

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From: Bo (bo_pfc@yahoo.com)
Date: Mon Feb 19 2001 - 18:20:04 PST



Hi Everybody, BO 2 0 2001-02-20T02:00:00Z 2001-02-20T02:00:00Z 2 702 4004 Yahoo 33 8 4917 9.2720 0 6 pt 6 pt 0
Hi Everybody,

 

I am interested in finding a way to easily estimate thequality of a package and its internal decoupling scheme with a decent level ofaccuracy.  

What I could probably do for a start is to look at the viasfor each power supply in the package and determine the total inductance forseveral paths inside of the package. What I mean by "path" is the total inductance that will beseen due to vias for a vias connecting a package ball to the internal packageplane designated for power supply A or path of vias connecting one side ofinternal decap to the power supply plane inside the package.  I would probably disregard the inductance ofthe package planes since they are typically not as inductive as the vias.  So fine given that I can accuratelycalculate via inductances through the package I could probably create a simpleSpice circuit that will recreate package inductances plus decouplingcapacitors.   Now what typically happensduring normal operation of a circuit is that current flows through powersupplies.  While circuit switches thesudden demand/change for/of the current will cause a voltage drop accross thepackage inductance (any!
one ever heard of "ground bounce"? :-) ).  So my questions are:  How to determine quality of the packagegiven this simple model?  Whatultimately person desires(me being one of them) is to determine if this packagewill be able to give less than X,Y,Z amounts of noise on the power supplies  A, B, C given that the chip containsgazillion transistors in its core and xxx number of HSTL I/O's, nnn number ofTTL I/O's, rrr number of LVDS I/O's, and PCI bus that is gg bits wide runningat frequency of www MHz.  Or what if Iincrease number of LVDS I/O's by 2 will the package still work?

The one option is to put a full chip model of the die thatcontains all these transistors, add a package model and run it.  Few billion years later you might getresult. If it ever converges of course. Other way is to somehow scale all the values in the circuit and try itthat way.   I have tried this andscaling is rather tricky.  It will giveyou better estimate as you make your model larger and larger.  But this will come at the cost of the speed.Yet another way is to use this simple package model, stick a current sourcesbetween power supply connection at the die and ground connection at the die andstart pumping current.  Hmmmm.  Is this right approach?  I have feeling that I am missingsomething.  And also I am not sure whatwould be correct values for current spikes in terms of switching rate as wellas amplitude.  They, current amplitudeand switching rate, will depend on the type of the I/O buffers and core of thechip, that is what I know.  But cansomeone suggest typical values?!
  Or howto find these values?  If I have morethan one power supply in the circuit should you also connect a current sourceto other poewr supplies the same way and then simulate?.  But if I want to find out which supplycauses most of the problems shouldn't be better to simulate only one powersupply drawing current while others remain "silent"?  And if they are "silent" what shouldbe connected to the die end of the power supply?  Any suggestions?

 

A simple diagram of a package

 

D

I

E

                                                    internal decap

       power supplydie                -------||--------         ground on the die

---------------||||-----------------------||||--------------|||||--------------------|||||--

                    |                                |                     |                             |

                    |                                |                     |                             |

 P                  |       Power Plane    |                     |                             |

A                  |---------|--------------|                    |                            | 

C                                |                                         |                             |

K                                |                                         |  Ground Plane   |

A                               |                                         |----|-----------------|

G                                |                                               |

E                                |                                              |                                         

                                  |                                               |

                                  |                                               |

-------------------------||||---------------------------------||||----------------                   

       power supplyon the pcb                 ground on thepcb

 

P

C

B

 

 

Any suggestions will be greatly appreciated.

 

Thank you for your time,

 

Regards,

Bo

 



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