Re: [SI-LIST] : Question regarding Host Bus simulation simulation

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From: Mike LaBonte (mike@labonte.com)
Date: Sat Feb 17 2001 - 09:06:46 PST


Rahul,

If you memory controller has open drain or open source
outputs, your buffer delay measurement fixture must
have a pullup or pulldown resistor and the correct
reference voltage.

You are no doubt using on-the-fly buffer delay
measurement, which places extra "test coupon" circuitry
in each simulation to get the design delays and standard
buffer delays in one shot. Open the memory controller
pin in the IbisDevice Editor, and use the Buffer Delays
window to set the test load conditions and simulate
the buffer delay right there. If you have to experiment
to get the test load info right, this will be faster
than running your net simulations over and over.

Mike LaBonte

whiz kid wrote:
>
> Hi SI Gurus,
>
> I have a question regarding the Host bus simulation.I
> am using spectraquest for doing the simulations .I am
> doing these simulations to find the min & max trace
> lengths .I am having no problems when the processor is
> driving .when the memeory controller is driving (In
> spectraquest I am measuring at the buffdely point.To
> my understanding this gives the wave form across the
> 50 ohm ref load) my wave form is a straight line
> instead of a clean pulse waveform.But at the driver
> pin it looks good .Also at the reciever pin the wave
> form is good .I am not able to figure out why this is
> happening.I am doing a fast case simulation .Am I
> missing some thing .
> Thanks in advance for your valuable advice.
> Rahul.
>
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