RE: [SI-LIST] : Memory timing calculations

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From: [email protected]
Date: Thu Feb 15 2001 - 10:29:48 PST

I don't have a copy of the PC133 spec., but in similar memory timing
I was able to successfully skew the clock between the devices to gain
at the expense of hold time. You can do this if with the new clock timing,
and the
minimum tco, the hold timing requirement is still met.


> -----Original Message-----
> From: Tom Pham [SMTP:[email protected]]
> Sent: Thursday, February 15, 2001 9:12 AM
> To: '[email protected]'; [email protected]
> Subject: RE: [SI-LIST] : Memory timing calculations
> I am having a same problem particularly with PC133 timing. PC133 spec.
> call
> for tco,max is 5.4ns and minimum setup margin of 1.5ns . For 133MHz, the
> period is 7.5ns so after you subtract 5.4ns and 1.5ns there is only 600ps
> left for Clk skew, trace delay etc which is not much to play with. Could
> anyone give recommendation what need to be done to meet setup requirement
> for PC133.
> Thanks.
> Tom Pham
> Calix Network
> -----Original Message-----
> From: [email protected] [mailto:[email protected]]
> Sent: Thursday, February 15, 2001 3:55 PM
> To: [email protected]
> Subject: [SI-LIST] : Memory timing calculations
> Hello All,
> I have a question related to memory signal simulations and validation of
> setup and hold timings.
> I have simulated the memory bus signals (pre-layout) between the 440BX
> and
> PC100
> registered DIMM. I have considered the IBIS model of the DIMM module for
> purpose of simulation.
> I have a set of timing equations for data and adrress/control signals for
> both corners.
> My simulated results meet the hold time, whereas setup time has not met.
> I would like to know anybody who has worked on the memory interface
> timings/simulations,
> so that I discuss these issues.
> Looking forward to your valued replies and suggestions.
> Regards
> Suchitha

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