Date: Thu Feb 15 2001 - 15:55:03 PST
I have a question related to memory signal simulations and validation of
setup and hold timings.
I have simulated the memory bus signals (pre-layout) between the 440BX and
registered DIMM. I have considered the IBIS model of the DIMM module for
purpose of simulation.
I have a set of timing equations for data and adrress/control signals for
My simulated results meet the hold time, whereas setup time has not met.
I would like to know anybody who has worked on the memory interface
so that I discuss these issues.
Looking forward to your valued replies and suggestions.
**** To unsubscribe from si-list or si-list-digest: send e-mail to
firstname.lastname@example.org. In the BODY of message put: UNSUBSCRIBE
si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
si-list archives are accessible at http://www.qsl.net/wb6tpu
This archive was generated by hypermail 2b29 : Tue May 08 2001 - 14:30:51 PDT