From: Ray Anderson ([email protected])
Date: Tue Feb 13 2001 - 15:25:09 PST
One thing to keep in mind, if you are interested in keeping your risetime
very fast, is to make sure you place the TDR sampling head as close
as possible to the device under test.
Any lossy lines (read that coax test leads) will degrade the risetime
output by the TDR to something that may be unacceptable for your purposes.
The 35ps risetime in a Tek SD-24 sampling head is very easily degraded
to several hundred ps (or worse) by a few feet of even high quality
coax. The solution is to use a sampling head extender cable that allows
you to place the sampling head right at the probe instead of several feet
Sun Microsystems Inc.
>We have capital to put together a TDR analysis capability for high speed
>interconnect characterization. our focus is mainly BGA, leadframe and high end
>1500+ I/O flip chip packages with interconnect length ranging from 2 mm to 20
>mm. As in any package construction vias, traces, solderballs, chip bumps etc
>make up a signal net.
>We are in the process of determining what equipment we would need to properly
>characterize interconnects ( at package level) with risetimes as low as 50~100
>picosecond. We would also include differential pair characterization as well
>since wee see the use of differential pairs at package level more and more.
>If you would send some feedback on your experience with TDR equipment, or a
>setup that works in high speed domain and provides good repeatibility, I would
>ver much appreciate your feedback.!.
>Thanks in advance
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