**From:** Eddie Suckow (*esuckow@spf.fairchildsemi.com*)

**Date:** Mon Feb 12 2001 - 07:57:25 PST

**Next message:**Bob Ross: "[SI-LIST] : EUROPEAN IBIS SUMMIT MEETING 2ND ANNOUNCEMENT"**Previous message:**Ritchey Lee: "Re: [SI-LIST] : Copper balance"

GTL modeling discussion:

A quick note to those interested in XTK GTL simulation. Fairchild Semiconductor has released its Ensigna Backplane Simulator allowing individuals to simulate numerous backplane configurations in a

matter of minutes.

Visit the link below for more information:

http://www.fairchildsemi.com/designcenter/labs/ensigna/index.html

In follow-up to Abe Riazi's discussion on calculating backplane impedance, it is important to remember the effect of loading the backplane if it is of parallel configuration. With the insertion of each

card a new capacitance is introduced, thus resulting in a decrease in the effective impedance. As multiple cards are inserted it is not uncommon to see the characteristic impedance of the backplane drop

by 25%. Naturally, this calls for a lower termination resistance Rt to keep the impedance matched. The challenge then becomes finding the optimum Rt for both unloaded and loaded backplane

configurations.

With VIL and VIH, a 50mV noise margin is extremely tight. I typically like to keep at least 150mV to ensure that a false trigger causing a glitch on the TTL output signal is not seen.

Eddie Suckow

Fairchild Semiconductor

GTLP Applications Engineer

esuckow@fairchildsemi.com

si-list-digest wrote:

*> si-list-digest Saturday, February 10 2001 Volume 01 : Number 415
*

*>
*

*> In this issue:
*

*>
*

*> 1.) Re: [SI-LIST] : GTL standard
*

*> "ARiazi" <ARIAZI@prodigy.net>
*

*>
*

*> ----------------------------------------------------------------------
*

*>
*

*> Date: Sat, 10 Feb 2001 15:50:19 -0800
*

*> From: "ARiazi" <ARIAZI@prodigy.net>
*

*> Subject: Re: [SI-LIST] : GTL standard
*

*>
*

*> Suchitha V Wrote:
*

*>
*

*> > First of all, Min, Typ, Max represent the SLOW, TYPICAL and FAST BUFFER
*

*> > CORNERS respectively.
*

*> > 2% implies that Vref can have a tolerance of +/- 2% on either side of the
*

*> > typical value.
*

*> > For the purpose of simulation, the SLOW, TYPICAL, and FAST buffer models
*

*> are
*

*> > included in the IBIS models
*

*> > which are derived from the SPICE simulations/measurements.
*

*> > SLOW corner is a buffer in its weak performance i.e, slow speed, weak
*

*> driver
*

*> > strength, weak voltage.
*

*> > In this case the variation of Vref= 2/3Vtt -2% is considered for deriving
*

*> > the VI data for the IBIS models.
*

*> >
*

*> > FAST corner is a buffer in its fullest performance i.e, fast speed, strong
*

*> > driver strength, strong voltage.
*

*> > In this case the variation of Vref=2/3Vtt +2% is considered for deriving
*

*> the
*

*> > VI data for the IBIS models.
*

*> >
*

*> > TYPICAL corner corner is a buffer with typical performance and therefore
*

*> > typical values are to be
*

*> > considered.
*

*> >
*

*> Hi Suchitha:
*

*> >
*

*> As you stated: "SLOW corner is a buffer in its weak performance i.e, slow
*

*> speed, weak driver strength, weak voltage".
*

*>
*

*> Additionally, temperature and package impedance also play a role so that:
*

*>
*

*> Slow Corner Model: slowest (Min) ramp (dV/dt), Min VI curves, Min voltage,
*

*> Max temperature, and Max package impedance.
*

*> Fast Corner Model: fastest ramp, Max VI, Max voltage, Min temperature, and
*

*> Min package impedance.
*

*> Typical Corner Model: All parameters at nominal values.
*

*>
*

*> In many cases, just a single set (i.e. Min, Typ, Max) of models
*

*> (representing each bus agent) proves sufficient for all signal quality and
*

*> timing margin evaluations. However, situations can arise which demand
*

*> multiple sets of models (of SAME component) for a comprehensive
*

*> investigations of overshoot/undershoot, crosstalk, synchronous timing skew,
*

*> etc. Furthermore, models often evolve through changes and revisions.
*

*> Therefore, care must be taken to obtain the most complete and recent models
*

*> for each simulation.
*

*>
*

*> The receiver input reference voltage ( Vref ) combined with a specified
*

*> tolerance dictate the input threshold region; i.e. :
*

*> VIL(max) = Vref - 50 mV
*

*> VIH(min) = Vref + 50 mV
*

*> The Input Low Voltage ( VIL ) and Input High Voltage ( VIH ) thresholds in
*

*> turn influence the lower and upper noise margins of the bus.
*

*> Furthermore, Vref in conjunction with a test load are used (by the processor
*

*> manufacturer) to specify the signals' valid timing parameters.
*

*> Consequently, for XTK simulations, the same test load should be utilized
*

*> for TIME_TO_VM calibration of Quad driver models with the
*

*> measurement voltage set at Vref.
*

*>
*

*> The termination voltage Vtt (equivalent to the processor core supply
*

*> voltage) also varies over a range of values. The smallest value of Vtt
*

*> should
*

*> be used in SS (i.e Slow buffer, Slow environment) and the largest Vtt value
*

*> in FF (i.e Fast buffer, Fast PCB) simulations.
*

*>
*

*> Vtt, Vref, noise margins, and the models are among critical considerations
*

*> when designing or simulating a high speed bus. Other essential bus elements
*

*> include topology, termination plans, stackup, decoupling techniques,
*

*> bus width, bandwidth, trace impedance, velocity, etc. The final paragraph
*

*> presents comments and examples regarding impedance and propagation delay.
*

*>
*

*> The formulas for computing bus impedance include numerous parameters
*

*> such as trace width, thickness, height over reference plane, substrate
*

*> dielectric constant, etc. Therefore, to efficiently verify for instance
*

*> 50 +/- 10% Ohms for GTL or 60 +/- 10% Ohms for PCI-X require
*

*> use of a field solver program. The signal propagation delay
*

*> Tpd (inverse of velocity) involves only the substrate dielectric constant
*

*> and simple equations:
*

*> Tpd = 1.017* SQRT(0.475Er + 0.67) nS/ft [For microstrip] and
*

*> Tpd = 1.017* SQRT(Er) nS/ft [For stripline traces]
*

*> For example, assuming FR-4 substrate and Er= 4.2, yields:
*

*> Tpd = 1.66 nS/ft [for microstrip] and
*

*> Tpd = 2.084 nS/ft [for stripline signals]
*

*> When analyzing a high speed bus, it is frequently desirable to ascertain a
*

*> range of Tpd values for the outer and inner traces. This can be easily
*

*> achieved by first assigning appropriate values to Er for the best and the
*

*> worst case corners and then applying the above Tpd equations.
*

*>
*

*> Best regards,
*

*>
*

*> Abe Riazi
*

*> ServerWorks.
*

*>
*

*> **** To unsubscribe from si-list or si-list-digest: send e-mail to
*

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*

*> ****
*

*>
*

*> ------------------------------
*

*>
*

*> End of si-list-digest V1 #415
*

*> *****************************
*

*>
*

*> **** To unsubscribe from si-list or si-list-digest: send e-mail to majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
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**Next message:**Bob Ross: "[SI-LIST] : EUROPEAN IBIS SUMMIT MEETING 2ND ANNOUNCEMENT"**Previous message:**Ritchey Lee: "Re: [SI-LIST] : Copper balance"

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