[SI-LIST] : Chip to Chip Clocking

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From: AMA (alokbya@yahoo.com)
Date: Thu Jan 25 2001 - 14:55:17 PST


Could any one shed some light on this topic. I am
used to two 2 clock topologies:
1- common clocks
2- Source synchronus

I recently heared about Chip to Chip distrubuted
clocking topology and have no ideas what it offers.

Adam Mrenaway

--- DORIN OPREA <dorin.oprea@alcatel.com> wrote:
> Broadside or edge coupled traces ? Mainly the choice
> is determined by the design
> requirements.
> I see the following case in which one would prefer
> broadside coupled:
> - signals require common mode immunity in which case
> single landed impedance is
> about 60 ohms
> - skin effect losses are critical (minimum 0.005"
> trace width)
> - minimum 2 signals layers are needed for routing;
> plane-signal-plane-signal-plane stackup would
> require more stackup thickness
> than plane-signal-signal-plane (allows also higher
> routing density)
> - mainly the signals are running in only one
> direction (backplane)
> - you may have have to connect a small pitch
> connector
> So long the broad side coupled traces are
> manufactured on a core construction
> the PCB vendors appear not have any issue with the
> trace alignment.
>
> Dorin
>
>
>
>
> "Heard, Chris" wrote:
>
> > Keeping Broadside pairs on Cores only is not
> practical in dense designs. A
> > 20 layer construction only has 3 transmission line
> constructions available
> > for Broadside routing. Broadside 50 ohm
> constructions always end up thicker
> > than edge-coupled, which drives thickness up and
> total available layer count
> > in a given mechanical design down. Increased
> thickness makes manufacturing
> > engineers angry and less layers makes pcb layout
> folks angry.
> >
> > If you don't have too many diff pairs, either way
> works. If your design has
> > a large quantity of diff pairs, broadside will
> make you crazy.
> >
> > Broadside on backplanes is a bad choice for
> similar reasons. Cores aren't
> > available at every construction, increased
> thickness drives up plated
> > through hole capacitance which dominates connector
> signal integrity. Wide
> > lines with low skin effect are difficult to use
> because achieving 100 ohms
> > differentially requires thicker construction...and
> on it goes.
> >
> > Chris
> >
> > -----Original Message-----
> > From: Scott McMorrow
> [mailto:scott@vasthorizons.com]
> > Sent: Saturday, January 20, 2001 2:17 AM
> > To: Ron Miller
> > Cc: Aubrey_Sparkman@dell.com;
> ldmiller@rhapsodynetworks.com;
> > ribrooks@nortelnetworks.com;
> SI-LIST@silab.eng.sun.com
> > Subject: Re: [SI-LIST] : Broadside v edge coupled
> striplines
> >
> > Ron,
> >
> > I would agree. Just trying to dispel the blanket
> statement that
> > broadside should be avoided due to manufacturing
> issues. There
> > are ways to engineer a board and reduce the
> tolerance issues
> > with broadside traces. Trace density is, of
> course, a seperate
> > issue.
> >
> > regards,
> >
> > scott
> >
> > --
> > Scott McMorrow
> > Principal Engineer
> > SiQual, Signal Quality Engineering
> > 18735 SW Boones Ferry Road
> > Tualatin, OR 97062-3090
> > (503) 885-1231
> > http://www.siqual.com
> >
> > Ron Miller wrote:
> >
> > > Hi scott
> > >
> > > Broadside lines require more real estate than
> edge coupled
> > > lines. If you have the real estate that is
> good. We do not.
> > >
> > > If you disagree the contention that broadside
> requires more
> > > real estate please e-mail me and I will fill in
> the details.
> > >
> > > ron Miller
> > >
> > > -----Original Message-----
> > > From: Scott McMorrow
> [mailto:scott@vasthorizons.com]
> > > Sent: Friday, January 19, 2001 10:00 AM
> > > To: Aubrey_Sparkman@Dell.com
> > > Cc: ldmiller@rhapsodynetworks.com;
> ribrooks@nortelnetworks.com;
> > > SI-LIST@silab.eng.sun.com
> > > Subject: Re: [SI-LIST] : Broadside v edge
> coupled striplines
> > >
> > > Aubrey,
> > >
> > > The manufacturing issues can be reduced by
> constructing the
> > > broadside pair on core material and keeping the
> spacing between
> > > the pairs small compared to the spacing to the
> planes. Then the
> > > separation between the pair is well controlled
> and the fields are
> > > well contained between the pairs.
> > >
> > > Another solution which works quite well is to
> use CPW or
> > > grounded CPW construction for diff pairs on
> outer layers.
> > >
> > > regards,
> > >
> > > scott
> > >
> > > --
> > > Scott McMorrow
> > > Principal Engineer
> > > SiQual, Signal Quality Engineering
> > > 18735 SW Boones Ferry Road
> > > Tualatin, OR 97062-3090
> > > (503) 885-1231
> > > http://www.siqual.com
> > >
> > > Aubrey_Sparkman@Dell.com wrote:
> > >
> > > > Thanks for that correction. Isn't the
> difference is really in
> > > > manufacturing, not physics? An EDGE-coupled
> diff pair is more uniform
> > > > because the pattern is etched in the same
> process. The
> > BROADSICE-coupled
> > > > diff pair is etched at two different times and
> additionally has to be
> > > > mechanically aligned for lamination. This
> adds two additional error
> > terms
> > > > to the accuracy of your BROADSICE-coupled diff
> pair that the
> > EDGE-coupled
> > > > diff pair does not have. So IMHO, you should
> really have a packing
> > density
> > > > problem before you consider using
> BROADSICE-coupled traces.
> > > >
> > > > But if you are doing work for Compaq or Sun,
> you should use
> > > > BROADSICE-coupled diff pairs whenever
> possible. :-)
> > > >
> > > > Aubrey Sparkman
> > > > Signal Integrity
> > > > Aubrey_Sparkman@Dell.com
> > > > (512) 723-3592
> > > >
> > > >
> > > >
> > >
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>
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