From: Jim Freeman ([email protected])
Date: Thu Jan 25 2001 - 13:27:55 PST
The first issue would be supply of power to the memories. There should be a worst
case power spec for the memories. Also, the metal widhs inside the memories fr power
should be measured to see if they are wide enough to supply power to the memories
without exceesing electromigration limits.
Sandy Taylor wrote:
> You have asked a question which requires significant detailed analysis.
> Other information you will need to approach this kind of problem is:
> - estimated core power
> - estimated I/O power
> - sheet resistivities
> - external and internal frequencies.
> - details of vertical stripe pitch per supply
> - details of horizontal power distribution.
> - circuit types and design style (static vs dynamic circuits, use of RAM etc)
> You can do "back of the envelope" calculations assuming uniform
> power distributions, but it is usually the details and the non standard
> areas that get you.
> Take a look at the software Simplex Solutions offers. They can extract
> the complete power grid, simulate the currents and solve for the IR
> drop everywhere on the chip. There several ways to analyze the problem
> offering trade offs in slight over design (faster static analysis) vs more precise
> dynamic simulations with longer run times.
> Their web site is:
> They have papers there on power planning (and other topics):
> Feel free to give me a call if you would like to talk about the details of
> these tools, I have been using the Simplex tools for several years.
> Sandy Taylor
> CMOS Solutions
> Olga Wa.
> (360) 376 3815
> Ajit Madhekar wrote:
> > Please check the chip image on my page.
> > http://home.talkcity.com/SonnetSt/ilikeajit/chip.jpg
> > Chip details
> > technology - 0.18 micron
> > Each vertical stripe 30 micron
> > chip 4900 x 4900 microns (200 mils x 200 mils) aprox.
> > cell count - 84 K cells
> > Power rings -- 2 rings of VDD and 2 rings of VSS at the 4 sides of the chip
> > of 30 micron each.
> > vertical stripes seen are power stripes with 30 micron width.
> > chip is fully digital ( No mixed signal )
> > 4 blocks seen are the memories in a chip
> > Total Pads = 244
> > No. of power pads -- around 43 ( 10 VDD 3.3 volts , 10 VDD 1.8 volts , 10
> > VSS 3.3V , 10 VSS 1.8V )
> > left 6 VDD, 9 VSS
> > bottom 6 VDD, 5 VSS
> > right 6 VDD, 4VSS
> > top 3 VDD, 4 VSS
> > Regards,
> > Ajit Madhekar
> > > Hi
> > > I am not sure whether this is a part of signal integrity but some of you
> > may
> > > be knowing this issue. So I tried here.
> > >
> > > I want to know about IR drop and how to avoid/minimize it.
> > > I am designing a chip at 0.18 micron and I am not sure whether it is
> > > affected by IR drop or not.
> > > So how can I make sure of this issue ?
> > >
> > > Thanks
> > > Ajit Madhekar
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