Re: [SI-LIST] : Broadside v edge coupled striplines

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From: Mike Jenkins (jenkins@lsil.com)
Date: Mon Jan 22 2001 - 10:57:57 PST


Ron,

If you don't mind, please put your responses to the SI reflector,
as I'm quite interested in the pros & cons of broadside coupling.
Like you, I think extra real estate and complexity are required.
For my part, this seems due to the need for thicker dielectrics
(and/or voiding one or more layers) as well as the complexity at
the ends.

I would like to hear your views.

Regards,
Mike

cadpro2k@dacafe.com wrote:
>
> Hi Ron,
>
> Could you provide me the details please? Also, what tool are you using
> to do your differential impedance calcs? I'm using Polar's CITS tool,
> but is there a better one? And, any additional references you have to DI
> would be appreciated.
>
> Thank you.
>
> Mitch Morey
> Sr PCB Designer
> San Diego, CA
>
> ---------Included Message----------
> > Date: Fri, 19 Jan 2001 17:18:08 -0800
> > From: "Ron Miller" <rmiller@brocade.com>
> > Reply-To: "Ron Miller" <rmiller@brocade.com>
> > To: "'Scott McMorrow'" <scott@vasthorizons.com>,
> <Aubrey_Sparkman@Dell.com>
> > Cc: <ldmiller@rhapsodynetworks.com>,
> <ribrooks@nortelnetworks.com>, <SI-LIST@silab.eng.sun.com>
> > Subject: RE: [SI-LIST] : Broadside v edge coupled striplines
> >
> > Hi scott
> >
> > Broadside lines require more real estate than edge coupled
> > lines. If you have the real estate that is good. We do not.
> >
> > If you disagree the contention that broadside requires more
> > real estate please e-mail me and I will fill in the details.
> >
> > ron Miller
> >
> > -----Original Message-----
> > From: Scott McMorrow [mailto:scott@vasthorizons.com]
> > Sent: Friday, January 19, 2001 10:00 AM
> > To: Aubrey_Sparkman@Dell.com
> > Cc: ldmiller@rhapsodynetworks.com; ribrooks@nortelnetworks.com;
> > SI-LIST@silab.eng.sun.com
> > Subject: Re: [SI-LIST] : Broadside v edge coupled striplines
> >
> >
> > Aubrey,
> >
> > The manufacturing issues can be reduced by constructing the
> > broadside pair on core material and keeping the spacing between
> > the pairs small compared to the spacing to the planes. Then the
> > separation between the pair is well controlled and the fields
> are
> > well contained between the pairs.
> >
> > Another solution which works quite well is to use CPW or
> > grounded CPW construction for diff pairs on outer layers.
> >
> >
> > regards,
> >
> > scott
> >
> > --
> > Scott McMorrow
> > Principal Engineer
> > SiQual, Signal Quality Engineering
> > 18735 SW Boones Ferry Road
> > Tualatin, OR 97062-3090
> > (503) 885-1231
> > http://www.siqual.com
> >
> >
> > Aubrey_Sparkman@Dell.com wrote:
> >
> > > Thanks for that correction. Isn't the difference is really in
> > > manufacturing, not physics? An EDGE-coupled diff pair is more
> uniform
> > > because the pattern is etched in the same process. The
> BROADSICE-coupled
> > > diff pair is etched at two different times and additionally has
> to be
> > > mechanically aligned for lamination. This adds two additional
> error terms
> > > to the accuracy of your BROADSICE-coupled diff pair that the
> EDGE-coupled
> > > diff pair does not have. So IMHO, you should really have a
> packing density
> > > problem before you consider using BROADSICE-coupled traces.
> > >
> > > But if you are doing work for Compaq or Sun, you should use
> > > BROADSICE-coupled diff pairs whenever possible. :-)
> > >
> > > Aubrey Sparkman
> > > Signal Integrity
> > > Aubrey_Sparkman@Dell.com
> > > (512) 723-3592
> > >
> > >
> > >
> >
> >
> >
> >
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-- 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 Mike Jenkins               Phone: 408.433.7901            _____     
 LSI Logic Corp, ms/G715      Fax: 408.433.7461        LSI|LOGIC| (R)   
 1525 McCarthy Blvd.       mailto:Jenkins@LSIL.com        |     |     
 Milpitas, CA  95035         http://www.lsilogic.com      |_____|    
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