From: Ajit Madhekar (firstname.lastname@example.org)
Date: Mon Jan 22 2001 - 02:17:24 PST
Please check the chip image on my page.
technology - 0.18 micron
Each vertical stripe 30 micron
chip 4900 x 4900 microns (200 mils x 200 mils) aprox.
cell count - 84 K cells
Power rings -- 2 rings of VDD and 2 rings of VSS at the 4 sides of the chip
of 30 micron each.
vertical stripes seen are power stripes with 30 micron width.
chip is fully digital ( No mixed signal )
4 blocks seen are the memories in a chip
Total Pads = 244
No. of power pads -- around 43 ( 10 VDD 3.3 volts , 10 VDD 1.8 volts , 10
VSS 3.3V , 10 VSS 1.8V )
left 6 VDD, 9 VSS
bottom 6 VDD, 5 VSS
right 6 VDD, 4VSS
top 3 VDD, 4 VSS
> I am not sure whether this is a part of signal integrity but some of you
> be knowing this issue. So I tried here.
> I want to know about IR drop and how to avoid/minimize it.
> I am designing a chip at 0.18 micron and I am not sure whether it is
> affected by IR drop or not.
> So how can I make sure of this issue ?
> Ajit Madhekar
**** To unsubscribe from si-list or si-list-digest: send e-mail to
email@example.com. In the BODY of message put: UNSUBSCRIBE
si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
si-list archives are accessible at http://www.qsl.net/wb6tpu
This archive was generated by hypermail 2b29 : Tue May 08 2001 - 14:30:41 PDT